// Automatically generated by genglobals.py
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// Automatically generated by genglobals.py
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// Module: control/clk_delay.v
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// Module: control/clk_delay.v
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wire hold_clk_iorq;
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wire hold_clk_iorq;
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wire hold_clk_wait;
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wire hold_clk_wait;
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wire iorq_Tw;
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wire iorq_Tw;
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wire busack;
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wire busack;
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wire pin_control_oe;
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wire pin_control_oe;
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wire hold_clk_busrq;
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wire hold_clk_busrq;
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// Module: control/decode_state.v
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// Module: control/decode_state.v
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wire in_halt;
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wire in_halt;
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wire table_cb;
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wire table_cb;
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wire table_ed;
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wire table_ed;
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wire table_xx;
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wire table_xx;
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wire use_ix;
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wire use_ix;
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wire use_ixiy;
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wire use_ixiy;
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wire in_alu;
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wire in_alu;
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wire repeat_en;
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wire repeat_en;
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// Module: control/exec_module.vh
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// Module: control/exec_module.vh
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wire ctl_state_iy_set;
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wire ctl_state_iy_set;
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wire ctl_state_ixiy_clr;
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wire ctl_state_ixiy_clr;
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wire ctl_state_ixiy_we;
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wire ctl_state_ixiy_we;
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wire ctl_state_halt_set;
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wire ctl_state_halt_set;
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wire ctl_state_tbl_clr;
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wire ctl_state_tbl_clr;
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wire ctl_state_tbl_ed_set;
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wire ctl_state_tbl_ed_set;
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wire ctl_state_tbl_cb_set;
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wire ctl_state_tbl_cb_set;
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wire ctl_state_alu;
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wire ctl_state_alu;
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wire ctl_repeat_we;
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wire ctl_repeat_we;
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wire ctl_iff1_iff2;
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wire ctl_iff1_iff2;
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wire ctl_iffx_we;
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wire ctl_iffx_we;
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wire ctl_iffx_bit;
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wire ctl_iffx_bit;
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wire ctl_im_we;
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wire ctl_im_we;
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wire ctl_no_ints;
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wire ctl_no_ints;
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wire ctl_ir_we;
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wire ctl_ir_we;
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wire ctl_mRead;
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wire ctl_mRead;
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wire ctl_mWrite;
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wire ctl_mWrite;
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wire ctl_iorw;
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wire ctl_iorw;
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wire ctl_shift_en;
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wire ctl_shift_en;
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wire ctl_daa_oe;
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wire ctl_daa_oe;
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wire ctl_alu_op_low;
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wire ctl_alu_op_low;
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wire ctl_cond_short;
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wire ctl_cond_short;
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wire ctl_alu_core_hf;
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wire ctl_alu_core_hf;
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wire ctl_eval_cond;
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wire ctl_eval_cond;
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wire ctl_66_oe;
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wire ctl_66_oe;
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wire [1:0] ctl_pf_sel;
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wire [1:0] ctl_pf_sel;
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wire ctl_alu_oe;
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wire ctl_alu_oe;
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wire ctl_alu_shift_oe;
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wire ctl_alu_shift_oe;
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wire ctl_alu_op2_oe;
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wire ctl_alu_op2_oe;
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wire ctl_alu_res_oe;
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wire ctl_alu_res_oe;
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wire ctl_alu_op1_oe;
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wire ctl_alu_op1_oe;
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wire ctl_alu_bs_oe;
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wire ctl_alu_bs_oe;
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wire ctl_alu_op1_sel_bus;
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wire ctl_alu_op1_sel_bus;
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wire ctl_alu_op1_sel_low;
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wire ctl_alu_op1_sel_low;
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wire ctl_alu_op1_sel_zero;
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wire ctl_alu_op1_sel_zero;
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wire ctl_alu_op2_sel_zero;
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wire ctl_alu_op2_sel_zero;
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wire ctl_alu_op2_sel_bus;
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wire ctl_alu_op2_sel_bus;
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wire ctl_alu_op2_sel_lq;
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wire ctl_alu_op2_sel_lq;
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wire ctl_alu_sel_op2_neg;
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wire ctl_alu_sel_op2_neg;
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wire ctl_alu_sel_op2_high;
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wire ctl_alu_sel_op2_high;
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wire ctl_alu_core_R;
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wire ctl_alu_core_R;
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wire ctl_alu_core_V;
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wire ctl_alu_core_V;
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wire ctl_alu_core_S;
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wire ctl_alu_core_S;
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wire ctl_flags_oe;
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wire ctl_flags_oe;
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wire ctl_flags_bus;
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wire ctl_flags_bus;
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wire ctl_flags_alu;
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wire ctl_flags_alu;
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wire ctl_flags_nf_set;
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wire ctl_flags_nf_set;
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wire ctl_flags_cf_set;
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wire ctl_flags_cf_set;
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wire ctl_flags_cf_cpl;
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wire ctl_flags_cf_cpl;
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wire ctl_flags_cf_we;
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wire ctl_flags_cf_we;
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wire ctl_flags_sz_we;
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wire ctl_flags_sz_we;
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wire ctl_flags_xy_we;
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wire ctl_flags_xy_we;
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wire ctl_flags_hf_we;
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wire ctl_flags_hf_we;
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wire ctl_flags_pf_we;
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wire ctl_flags_pf_we;
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wire ctl_flags_nf_we;
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wire ctl_flags_nf_we;
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wire ctl_flags_cf2_we;
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wire ctl_flags_cf2_we;
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wire ctl_flags_hf_cpl;
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wire ctl_flags_hf_cpl;
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wire ctl_flags_use_cf2;
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wire ctl_flags_use_cf2;
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wire ctl_flags_hf2_we;
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wire ctl_flags_hf2_we;
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wire ctl_flags_nf_clr;
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wire ctl_flags_nf_clr;
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wire ctl_alu_zero_16bit;
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wire ctl_alu_zero_16bit;
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wire [1:0] ctl_flags_cf2_sel;
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wire ctl_flags_cf2_sel_shift;
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wire ctl_sw_4d;
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wire ctl_flags_cf2_sel_daa;
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wire ctl_sw_4u;
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wire ctl_sw_4u;
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wire ctl_reg_in_hi;
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wire ctl_reg_in_hi;
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wire ctl_reg_in_lo;
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wire ctl_reg_in_lo;
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wire ctl_reg_out_lo;
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wire ctl_reg_out_lo;
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wire ctl_reg_out_hi;
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wire ctl_reg_out_hi;
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wire ctl_reg_exx;
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wire ctl_reg_exx;
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wire ctl_reg_ex_af;
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wire ctl_reg_ex_af;
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wire ctl_reg_ex_de_hl;
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wire ctl_reg_ex_de_hl;
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wire ctl_reg_use_sp;
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wire ctl_reg_use_sp;
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wire ctl_reg_sel_pc;
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wire ctl_reg_sel_pc;
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wire ctl_reg_sel_ir;
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wire ctl_reg_sel_ir;
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wire ctl_reg_sel_wz;
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wire ctl_reg_sel_wz;
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wire ctl_reg_gp_we;
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wire ctl_reg_gp_we;
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wire ctl_reg_not_pc;
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wire ctl_reg_not_pc;
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wire ctl_reg_sys_we_lo;
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wire ctl_reg_sys_we_lo;
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wire ctl_reg_sys_we_hi;
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wire ctl_reg_sys_we_hi;
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wire ctl_reg_sys_we;
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wire ctl_reg_sys_we;
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wire ctl_sw_4d;
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wire [1:0] ctl_reg_gp_hilo;
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wire [1:0] ctl_reg_gp_hilo;
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wire [1:0] ctl_reg_gp_sel;
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wire [1:0] ctl_reg_gp_sel;
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wire [1:0] ctl_reg_sys_hilo;
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wire [1:0] ctl_reg_sys_hilo;
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wire ctl_inc_cy;
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wire ctl_inc_cy;
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wire ctl_inc_dec;
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wire ctl_inc_dec;
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wire ctl_inc_zero;
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wire ctl_al_we;
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wire ctl_al_we;
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wire ctl_inc_limit6;
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wire ctl_inc_limit6;
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wire ctl_bus_inc_oe;
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wire ctl_bus_inc_oe;
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wire ctl_apin_mux;
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wire ctl_apin_mux;
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wire ctl_apin_mux2;
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wire ctl_apin_mux2;
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wire ctl_bus_ff_oe;
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wire ctl_bus_ff_oe;
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wire ctl_bus_zero_oe;
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wire ctl_bus_zero_oe;
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wire ctl_bus_db_oe;
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wire ctl_sw_1u;
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wire ctl_sw_1u;
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wire ctl_sw_1d;
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wire ctl_sw_1d;
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wire ctl_sw_2u;
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wire ctl_sw_2u;
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wire ctl_sw_2d;
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wire ctl_sw_2d;
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wire ctl_sw_mask543_en;
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wire ctl_sw_mask543_en;
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wire ctl_bus_db_we;
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wire ctl_bus_db_we;
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wire ctl_bus_db_oe;
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// Module: control/execute.sv
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// Module: control/execute.v
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wire nextM;
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wire nextM;
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wire setM1;
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wire setM1;
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wire fFetch;
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wire fFetch;
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wire fMRead;
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wire fMRead;
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wire fMWrite;
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wire fMWrite;
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wire fIORead;
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wire fIORead;
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wire fIOWrite;
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wire fIOWrite;
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// Module: control/interrupts.v
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// Module: control/interrupts.v
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wire iff1;
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wire iff2;
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wire iff2;
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wire im1;
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wire im1;
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wire im2;
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wire im2;
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wire in_nmi;
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wire in_nmi;
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wire in_intr;
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wire in_intr;
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// Module: control/ir.v
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// Module: control/ir.v
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wire [7:0] opcode;
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wire [7:0] opcode;
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// Module: control/pin_control.v
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// Module: control/pin_control.v
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wire bus_ab_pin_we;
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wire bus_ab_pin_we;
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wire bus_db_pin_oe;
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wire bus_db_pin_oe;
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wire bus_db_pin_re;
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wire bus_db_pin_re;
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// Module: control/pla_decode.sv
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// Module: control/pla_decode.v
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wire [104:0] pla;
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wire [104:0] pla;
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// Module: control/resets.v
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// Module: control/resets.v
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wire clrpc;
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wire clrpc;
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wire nreset;
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wire nreset;
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// Module: control/memory_ifc.v
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// Module: control/memory_ifc.v
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wire nM1_out;
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wire nM1_out;
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wire nRFSH_out;
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wire nRFSH_out;
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wire nMREQ_out;
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wire nMREQ_out;
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wire nRD_out;
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wire nRD_out;
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wire nWR_out;
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wire nWR_out;
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wire nIORQ_out;
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wire nIORQ_out;
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wire latch_wait;
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wire latch_wait;
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// Module: control/sequencer.v
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// Module: control/sequencer.v
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wire M1;
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wire M1;
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wire M2;
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wire M2;
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wire M3;
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wire M3;
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wire M4;
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wire M4;
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wire M5;
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wire M5;
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wire M6;
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wire T1;
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wire T1;
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wire T2;
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wire T2;
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wire T3;
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wire T3;
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wire T4;
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wire T4;
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wire T5;
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wire T5;
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wire T6;
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wire T6;
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wire timings_en;
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wire timings_en;
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// Module: alu/alu_control.v
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// Module: alu/alu_control.v
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wire alu_shift_in;
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wire alu_shift_in;
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wire alu_shift_right;
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wire alu_shift_right;
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wire alu_shift_left;
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wire alu_shift_left;
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wire shift_cf_out;
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wire shift_cf_out;
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wire alu_parity_in;
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wire alu_parity_in;
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wire flags_cond_true;
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wire flags_cond_true;
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wire daa_cf_out;
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wire daa_cf_out;
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wire pf_sel;
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wire pf_sel;
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wire alu_op_low;
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wire alu_op_low;
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wire alu_core_cf_in;
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wire alu_core_cf_in;
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wire [7:0] db;
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wire [7:0] db;
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// Module: alu/alu_select.v
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// Module: alu/alu_select.v
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wire alu_oe;
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wire alu_oe;
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wire alu_shift_oe;
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wire alu_shift_oe;
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wire alu_op2_oe;
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wire alu_op2_oe;
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wire alu_res_oe;
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wire alu_res_oe;
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wire alu_op1_oe;
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wire alu_op1_oe;
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wire alu_bs_oe;
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wire alu_bs_oe;
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wire alu_op1_sel_bus;
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wire alu_op1_sel_bus;
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wire alu_op1_sel_low;
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wire alu_op1_sel_low;
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wire alu_op1_sel_zero;
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wire alu_op1_sel_zero;
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wire alu_op2_sel_zero;
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wire alu_op2_sel_zero;
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wire alu_op2_sel_bus;
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wire alu_op2_sel_bus;
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wire alu_op2_sel_lq;
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wire alu_op2_sel_lq;
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wire alu_sel_op2_neg;
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wire alu_sel_op2_neg;
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wire alu_sel_op2_high;
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wire alu_sel_op2_high;
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wire alu_core_R;
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wire alu_core_R;
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wire alu_core_V;
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wire alu_core_V;
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wire alu_core_S;
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wire alu_core_S;
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// Module: alu/alu_flags.v
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// Module: alu/alu_flags.v
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wire flags_sf;
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wire flags_sf;
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wire flags_zf;
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wire flags_zf;
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wire flags_hf;
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wire flags_hf;
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wire flags_pf;
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wire flags_pf;
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wire flags_cf;
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wire flags_cf;
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wire flags_nf;
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wire flags_nf;
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wire flags_cf_latch;
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wire flags_cf_latch;
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wire flags_hf2;
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wire flags_hf2;
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// Module: alu/alu.v
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// Module: alu/alu.v
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wire alu_zero;
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wire alu_zero;
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wire alu_parity_out;
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wire alu_parity_out;
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wire alu_high_eq_9;
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wire alu_high_eq_9;
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wire alu_high_gt_9;
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wire alu_high_gt_9;
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wire alu_low_gt_9;
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wire alu_low_gt_9;
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wire alu_shift_db0;
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wire alu_shift_db0;
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wire alu_shift_db7;
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wire alu_shift_db7;
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wire alu_core_cf_out;
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wire alu_core_cf_out;
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wire alu_sf_out;
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wire alu_sf_out;
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wire alu_yf_out;
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wire alu_yf_out;
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wire alu_xf_out;
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wire alu_xf_out;
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wire alu_vf_out;
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wire alu_vf_out;
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wire [3:0] test_db_high;
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wire [3:0] test_db_high;
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wire [3:0] test_db_low;
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wire [3:0] test_db_low;
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// Module: registers/reg_control.v
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// Module: registers/reg_control.v
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wire reg_sel_bc;
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wire reg_sel_bc;
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wire reg_sel_bc2;
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wire reg_sel_bc2;
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wire reg_sel_ix;
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wire reg_sel_ix;
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wire reg_sel_iy;
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wire reg_sel_iy;
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wire reg_sel_de;
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wire reg_sel_de;
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wire reg_sel_hl;
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wire reg_sel_hl;
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wire reg_sel_de2;
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wire reg_sel_de2;
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wire reg_sel_hl2;
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wire reg_sel_hl2;
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wire reg_sel_af;
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wire reg_sel_af;
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wire reg_sel_af2;
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wire reg_sel_af2;
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wire reg_sel_wz;
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wire reg_sel_wz;
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wire reg_sel_pc;
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wire reg_sel_pc;
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wire reg_sel_ir;
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wire reg_sel_ir;
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wire reg_sel_sp;
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wire reg_sel_sp;
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wire reg_sel_gp_hi;
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wire reg_sel_gp_hi;
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wire reg_sel_gp_lo;
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wire reg_sel_gp_lo;
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wire reg_sel_sys_lo;
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wire reg_sel_sys_lo;
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wire reg_sel_sys_hi;
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wire reg_sel_sys_hi;
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wire reg_gp_we;
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wire reg_gp_we;
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wire reg_sys_we_lo;
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wire reg_sys_we_lo;
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wire reg_sys_we_hi;
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wire reg_sys_we_hi;
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wire reg_sw_4d_lo;
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wire reg_sw_4d_hi;
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// Module: bus/address_latch.v
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// Module: bus/address_latch.v
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wire address_is_1;
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wire address_is_1;
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wire [15:0] address;
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wire [15:0] address;
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// Module: bus/address_pins.v
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// Module: bus/address_pins.v
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wire [15:0] abus;
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wire [15:0] abus;
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// Module: bus/bus_control.v
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// Module: bus/bus_switch.v
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wire bus_db_oe;
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// Module: bus/bus_switch.sv
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wire bus_sw_1u;
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wire bus_sw_1u;
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wire bus_sw_1d;
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wire bus_sw_1d;
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wire bus_sw_2u;
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wire bus_sw_2u;
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wire bus_sw_2d;
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wire bus_sw_2d;
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wire bus_sw_mask543_en;
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wire bus_sw_mask543_en;
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// Module: bus/control_pins_n.v
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// Module: bus/control_pins_n.v
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wire nmi;
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wire nmi;
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wire busrq;
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wire busrq;
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wire clk;
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wire clk;
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wire intr;
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wire intr;
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wire mwait;
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wire mwait;
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wire reset_in;
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wire reset_in;
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wire pin_nM1;
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wire pin_nM1;
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wire pin_nMREQ;
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wire pin_nMREQ;
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wire pin_nIORQ;
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wire pin_nIORQ;
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wire pin_nRD;
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wire pin_nRD;
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wire pin_nWR;
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wire pin_nWR;
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wire pin_nRFSH;
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wire pin_nRFSH;
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wire pin_nHALT;
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wire pin_nHALT;
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wire pin_nBUSACK;
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wire pin_nBUSACK;
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