OpenCores
URL https://opencores.org/ocsvn/a-z80/a-z80/trunk

Subversion Repositories a-z80

[/] [a-z80/] [trunk/] [cpu/] [toplevel/] [test_fuse.vh] - Diff between revs 8 and 13

Show entire file | Details | Blame | View Log

Rev 8 Rev 13
Line 2... Line 2...
 
 
force dut.resets_.clrpc=0;
force dut.resets_.clrpc=0;
force dut.reg_file_.reg_gp_we=0;
force dut.reg_file_.reg_gp_we=0;
force dut.reg_control_.ctl_reg_sys_we=0;
force dut.reg_control_.ctl_reg_sys_we=0;
force dut.z80_top_ifc_n.fpga_reset=1;
force dut.z80_top_ifc_n.fpga_reset=1;
#2
#2 // Start test loop
//--------------------------------------------------------------------------------
 
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.db=0;
   force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
#2 release dut.ir_.ctl_ir_we;
   release dut.ir_.db;
   release dut.ir_.db;
$fdisplay(f,"Testing opcode 00      NOP");
$fdisplay(f,"Testing opcode 00      NOP");
Line 141... Line 141...
   ram.Mem[0] = 8'h00;
   ram.Mem[0] = 8'h00;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.address_latch_.Q=16'h0000;
   force dut.address_latch_.Q=16'h0000;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_file_.reg_gp_we;
   release dut.reg_file_.reg_gp_we;
#3
#2 // Execute: M1/T1 start
   release dut.address_latch_.Q;
#1 release dut.address_latch_.Q;
#1
#1
#6 // Execute
#6 // Wait for opcode end
   force dut.reg_control_.ctl_reg_sys_we=0;
   force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2 pc=z.A;
#2
#2
#1 force dut.reg_file_.reg_gp_we=0;
#1 force dut.reg_file_.reg_gp_we=0;
   force dut.z80_top_ifc_n.fpga_reset=1;
   force dut.z80_top_ifc_n.fpga_reset=1;
Line 175... Line 175...
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
 
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.db=0;
   force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
#2 release dut.ir_.ctl_ir_we;
   release dut.ir_.db;
   release dut.ir_.db;
$fdisplay(f,"Testing opcode ed67    RRD");
$fdisplay(f,"Testing opcode ed67    RRD");
Line 316... Line 317...
   ram.Mem[47582] = 8'h93;
   ram.Mem[47582] = 8'h93;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.address_latch_.Q=16'h0000;
   force dut.address_latch_.Q=16'h0000;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_file_.reg_gp_we;
   release dut.reg_file_.reg_gp_we;
#3
#2 // Execute: M1/T1 start
   release dut.address_latch_.Q;
#1 release dut.address_latch_.Q;
#1
#1
#34 // Execute
#34 // Wait for opcode end
   force dut.reg_control_.ctl_reg_sys_we=0;
   force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2 pc=z.A;
#2
#2
#1 force dut.reg_file_.reg_gp_we=0;
#1 force dut.reg_file_.reg_gp_we=0;
   force dut.z80_top_ifc_n.fpga_reset=1;
   force dut.z80_top_ifc_n.fpga_reset=1;
Line 351... Line 352...
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
   if (ram.Mem[47582]!==8'h69) $fdisplay(f,"* Mem[b9de]=%h !=69",ram.Mem[47582]);
   if (ram.Mem[47582]!==8'h69) $fdisplay(f,"* Mem[b9de]=%h !=69",ram.Mem[47582]);
//--------------------------------------------------------------------------------
#1 // End opcode
 
 
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.db=0;
   force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
#2 release dut.ir_.ctl_ir_we;
   release dut.ir_.db;
   release dut.ir_.db;
$fdisplay(f,"Testing opcode ed6f    RLD");
$fdisplay(f,"Testing opcode ed6f    RLD");
Line 492... Line 494...
   ram.Mem[16444] = 8'hc4;
   ram.Mem[16444] = 8'hc4;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.address_latch_.Q=16'h0000;
   force dut.address_latch_.Q=16'h0000;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_file_.reg_gp_we;
   release dut.reg_file_.reg_gp_we;
#3
#2 // Execute: M1/T1 start
   release dut.address_latch_.Q;
#1 release dut.address_latch_.Q;
#1
#1
#34 // Execute
#34 // Wait for opcode end
   force dut.reg_control_.ctl_reg_sys_we=0;
   force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2 pc=z.A;
#2
#2
#1 force dut.reg_file_.reg_gp_we=0;
#1 force dut.reg_file_.reg_gp_we=0;
   force dut.z80_top_ifc_n.fpga_reset=1;
   force dut.z80_top_ifc_n.fpga_reset=1;
Line 527... Line 529...
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
   if (ram.Mem[16444]!==8'h45) $fdisplay(f,"* Mem[403c]=%h !=45",ram.Mem[16444]);
   if (ram.Mem[16444]!==8'h45) $fdisplay(f,"* Mem[403c]=%h !=45",ram.Mem[16444]);
//--------------------------------------------------------------------------------
#1 // End opcode
 
 
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.db=0;
   force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
#2 release dut.ir_.ctl_ir_we;
   release dut.ir_.db;
   release dut.ir_.db;
$fdisplay(f,"Testing opcode 81      ADD A,C");
$fdisplay(f,"Testing opcode 81      ADD A,C");
Line 667... Line 670...
   ram.Mem[56486] = 8'h49;
   ram.Mem[56486] = 8'h49;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.address_latch_.Q=16'h0000;
   force dut.address_latch_.Q=16'h0000;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_file_.reg_gp_we;
   release dut.reg_file_.reg_gp_we;
#3
#2 // Execute: M1/T1 start
   release dut.address_latch_.Q;
#1 release dut.address_latch_.Q;
#1
#1
#6 // Execute
#6 // Wait for opcode end
   force dut.reg_control_.ctl_reg_sys_we=0;
   force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2 pc=z.A;
#2
#2
#1 force dut.reg_file_.reg_gp_we=0;
#1 force dut.reg_file_.reg_gp_we=0;
   force dut.z80_top_ifc_n.fpga_reset=1;
   force dut.z80_top_ifc_n.fpga_reset=1;
Line 701... Line 704...
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
 
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.db=0;
   force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
#2 release dut.ir_.ctl_ir_we;
   release dut.ir_.db;
   release dut.ir_.db;
$fdisplay(f,"Testing opcode cb41    BIT 0,C");
$fdisplay(f,"Testing opcode cb41    BIT 0,C");
Line 842... Line 846...
   ram.Mem[31721] = 8'hf7;
   ram.Mem[31721] = 8'hf7;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.address_latch_.Q=16'h0000;
   force dut.address_latch_.Q=16'h0000;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_file_.reg_gp_we;
   release dut.reg_file_.reg_gp_we;
#3
#2 // Execute: M1/T1 start
   release dut.address_latch_.Q;
#1 release dut.address_latch_.Q;
#1
#1
#14 // Execute
#14 // Wait for opcode end
   force dut.reg_control_.ctl_reg_sys_we=0;
   force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2 pc=z.A;
#2
#2
#1 force dut.reg_file_.reg_gp_we=0;
#1 force dut.reg_file_.reg_gp_we=0;
   force dut.z80_top_ifc_n.fpga_reset=1;
   force dut.z80_top_ifc_n.fpga_reset=1;
Line 876... Line 880...
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
 
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.db=0;
   force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
#2 release dut.ir_.ctl_ir_we;
   release dut.ir_.db;
   release dut.ir_.db;
$fdisplay(f,"Testing opcode cb93    RES 2,E");
$fdisplay(f,"Testing opcode cb93    RES 2,E");
Line 1017... Line 1022...
   ram.Mem[8756] = 8'ha0;
   ram.Mem[8756] = 8'ha0;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.address_latch_.Q=16'h0000;
   force dut.address_latch_.Q=16'h0000;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_file_.reg_gp_we;
   release dut.reg_file_.reg_gp_we;
#3
#2 // Execute: M1/T1 start
   release dut.address_latch_.Q;
#1 release dut.address_latch_.Q;
#1
#1
#14 // Execute
#14 // Wait for opcode end
   force dut.reg_control_.ctl_reg_sys_we=0;
   force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2 pc=z.A;
#2
#2
#1 force dut.reg_file_.reg_gp_we=0;
#1 force dut.reg_file_.reg_gp_we=0;
   force dut.z80_top_ifc_n.fpga_reset=1;
   force dut.z80_top_ifc_n.fpga_reset=1;
Line 1051... Line 1056...
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
 
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.db=0;
   force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
#2 release dut.ir_.ctl_ir_we;
   release dut.ir_.db;
   release dut.ir_.db;
$fdisplay(f,"Testing opcode cbe5    SET 4,L");
$fdisplay(f,"Testing opcode cbe5    SET 4,L");
Line 1192... Line 1198...
   ram.Mem[46223] = 8'hcf;
   ram.Mem[46223] = 8'hcf;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.address_latch_.Q=16'h0000;
   force dut.address_latch_.Q=16'h0000;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_file_.reg_gp_we;
   release dut.reg_file_.reg_gp_we;
#3
#2 // Execute: M1/T1 start
   release dut.address_latch_.Q;
#1 release dut.address_latch_.Q;
#1
#1
#14 // Execute
#14 // Wait for opcode end
   force dut.reg_control_.ctl_reg_sys_we=0;
   force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2 pc=z.A;
#2
#2
#1 force dut.reg_file_.reg_gp_we=0;
#1 force dut.reg_file_.reg_gp_we=0;
   force dut.z80_top_ifc_n.fpga_reset=1;
   force dut.z80_top_ifc_n.fpga_reset=1;
Line 1226... Line 1232...
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
 
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.db=0;
   force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
#2 release dut.ir_.ctl_ir_we;
   release dut.ir_.db;
   release dut.ir_.db;
$fdisplay(f,"Testing opcode 8c      ADC A,H");
$fdisplay(f,"Testing opcode 8c      ADC A,H");
Line 1366... Line 1373...
   ram.Mem[56486] = 8'h49;
   ram.Mem[56486] = 8'h49;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.address_latch_.Q=16'h0000;
   force dut.address_latch_.Q=16'h0000;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_file_.reg_gp_we;
   release dut.reg_file_.reg_gp_we;
#3
#2 // Execute: M1/T1 start
   release dut.address_latch_.Q;
#1 release dut.address_latch_.Q;
#1
#1
#6 // Execute
#6 // Wait for opcode end
   force dut.reg_control_.ctl_reg_sys_we=0;
   force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2 pc=z.A;
#2
#2
#1 force dut.reg_file_.reg_gp_we=0;
#1 force dut.reg_file_.reg_gp_we=0;
   force dut.z80_top_ifc_n.fpga_reset=1;
   force dut.z80_top_ifc_n.fpga_reset=1;
Line 1400... Line 1407...
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
 
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.db=0;
   force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
#2 release dut.ir_.ctl_ir_we;
   release dut.ir_.db;
   release dut.ir_.db;
$fdisplay(f,"Testing opcode 92      SUB D");
$fdisplay(f,"Testing opcode 92      SUB D");
Line 1540... Line 1548...
   ram.Mem[56486] = 8'h49;
   ram.Mem[56486] = 8'h49;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.address_latch_.Q=16'h0000;
   force dut.address_latch_.Q=16'h0000;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_file_.reg_gp_we;
   release dut.reg_file_.reg_gp_we;
#3
#2 // Execute: M1/T1 start
   release dut.address_latch_.Q;
#1 release dut.address_latch_.Q;
#1
#1
#6 // Execute
#6 // Wait for opcode end
   force dut.reg_control_.ctl_reg_sys_we=0;
   force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2 pc=z.A;
#2
#2
#1 force dut.reg_file_.reg_gp_we=0;
#1 force dut.reg_file_.reg_gp_we=0;
   force dut.z80_top_ifc_n.fpga_reset=1;
   force dut.z80_top_ifc_n.fpga_reset=1;
Line 1574... Line 1582...
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
 
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.db=0;
   force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
#2 release dut.ir_.ctl_ir_we;
   release dut.ir_.db;
   release dut.ir_.db;
$fdisplay(f,"Testing opcode 9d      SBC A,L");
$fdisplay(f,"Testing opcode 9d      SBC A,L");
Line 1714... Line 1723...
   ram.Mem[56486] = 8'h49;
   ram.Mem[56486] = 8'h49;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.address_latch_.Q=16'h0000;
   force dut.address_latch_.Q=16'h0000;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_file_.reg_gp_we;
   release dut.reg_file_.reg_gp_we;
#3
#2 // Execute: M1/T1 start
   release dut.address_latch_.Q;
#1 release dut.address_latch_.Q;
#1
#1
#6 // Execute
#6 // Wait for opcode end
   force dut.reg_control_.ctl_reg_sys_we=0;
   force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2 pc=z.A;
#2
#2
#1 force dut.reg_file_.reg_gp_we=0;
#1 force dut.reg_file_.reg_gp_we=0;
   force dut.z80_top_ifc_n.fpga_reset=1;
   force dut.z80_top_ifc_n.fpga_reset=1;
Line 1748... Line 1757...
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
 
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.db=0;
   force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
#2 release dut.ir_.ctl_ir_we;
   release dut.ir_.db;
   release dut.ir_.db;
$fdisplay(f,"Testing opcode a3      AND E");
$fdisplay(f,"Testing opcode a3      AND E");
Line 1888... Line 1898...
   ram.Mem[56486] = 8'h49;
   ram.Mem[56486] = 8'h49;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.address_latch_.Q=16'h0000;
   force dut.address_latch_.Q=16'h0000;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_file_.reg_gp_we;
   release dut.reg_file_.reg_gp_we;
#3
#2 // Execute: M1/T1 start
   release dut.address_latch_.Q;
#1 release dut.address_latch_.Q;
#1
#1
#6 // Execute
#6 // Wait for opcode end
   force dut.reg_control_.ctl_reg_sys_we=0;
   force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2 pc=z.A;
#2
#2
#1 force dut.reg_file_.reg_gp_we=0;
#1 force dut.reg_file_.reg_gp_we=0;
   force dut.z80_top_ifc_n.fpga_reset=1;
   force dut.z80_top_ifc_n.fpga_reset=1;
Line 1922... Line 1932...
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
 
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.db=0;
   force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
#2 release dut.ir_.ctl_ir_we;
   release dut.ir_.db;
   release dut.ir_.db;
$fdisplay(f,"Testing opcode ae      XOR (HL)");
$fdisplay(f,"Testing opcode ae      XOR (HL)");
Line 2062... Line 2073...
   ram.Mem[56486] = 8'h49;
   ram.Mem[56486] = 8'h49;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.address_latch_.Q=16'h0000;
   force dut.address_latch_.Q=16'h0000;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_file_.reg_gp_we;
   release dut.reg_file_.reg_gp_we;
#3
#2 // Execute: M1/T1 start
   release dut.address_latch_.Q;
#1 release dut.address_latch_.Q;
#1
#1
#12 // Execute
#12 // Wait for opcode end
   force dut.reg_control_.ctl_reg_sys_we=0;
   force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2 pc=z.A;
#2
#2
#1 force dut.reg_file_.reg_gp_we=0;
#1 force dut.reg_file_.reg_gp_we=0;
   force dut.z80_top_ifc_n.fpga_reset=1;
   force dut.z80_top_ifc_n.fpga_reset=1;
Line 2096... Line 2107...
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
 
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.db=0;
   force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
#2 release dut.ir_.ctl_ir_we;
   release dut.ir_.db;
   release dut.ir_.db;
$fdisplay(f,"Testing opcode b4      OR H");
$fdisplay(f,"Testing opcode b4      OR H");
Line 2236... Line 2248...
   ram.Mem[56486] = 8'h49;
   ram.Mem[56486] = 8'h49;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.address_latch_.Q=16'h0000;
   force dut.address_latch_.Q=16'h0000;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_file_.reg_gp_we;
   release dut.reg_file_.reg_gp_we;
#3
#2 // Execute: M1/T1 start
   release dut.address_latch_.Q;
#1 release dut.address_latch_.Q;
#1
#1
#6 // Execute
#6 // Wait for opcode end
   force dut.reg_control_.ctl_reg_sys_we=0;
   force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2 pc=z.A;
#2
#2
#1 force dut.reg_file_.reg_gp_we=0;
#1 force dut.reg_file_.reg_gp_we=0;
   force dut.z80_top_ifc_n.fpga_reset=1;
   force dut.z80_top_ifc_n.fpga_reset=1;
Line 2270... Line 2282...
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
 
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.db=0;
   force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
#2 release dut.ir_.ctl_ir_we;
   release dut.ir_.db;
   release dut.ir_.db;
$fdisplay(f,"Testing opcode bf      CP A");
$fdisplay(f,"Testing opcode bf      CP A");
Line 2410... Line 2423...
   ram.Mem[56486] = 8'h49;
   ram.Mem[56486] = 8'h49;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.address_latch_.Q=16'h0000;
   force dut.address_latch_.Q=16'h0000;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_file_.reg_gp_we;
   release dut.reg_file_.reg_gp_we;
#3
#2 // Execute: M1/T1 start
   release dut.address_latch_.Q;
#1 release dut.address_latch_.Q;
#1
#1
#6 // Execute
#6 // Wait for opcode end
   force dut.reg_control_.ctl_reg_sys_we=0;
   force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2 pc=z.A;
#2
#2
#1 force dut.reg_file_.reg_gp_we=0;
#1 force dut.reg_file_.reg_gp_we=0;
   force dut.z80_top_ifc_n.fpga_reset=1;
   force dut.z80_top_ifc_n.fpga_reset=1;
Line 2444... Line 2457...
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
 
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.db=0;
   force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
#2 release dut.ir_.ctl_ir_we;
   release dut.ir_.db;
   release dut.ir_.db;
$fdisplay(f,"Testing opcode 43      LD B,E");
$fdisplay(f,"Testing opcode 43      LD B,E");
Line 2584... Line 2598...
   ram.Mem[41321] = 8'h50;
   ram.Mem[41321] = 8'h50;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.address_latch_.Q=16'h0000;
   force dut.address_latch_.Q=16'h0000;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_file_.reg_gp_we;
   release dut.reg_file_.reg_gp_we;
#3
#2 // Execute: M1/T1 start
   release dut.address_latch_.Q;
#1 release dut.address_latch_.Q;
#1
#1
#6 // Execute
#6 // Wait for opcode end
   force dut.reg_control_.ctl_reg_sys_we=0;
   force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2 pc=z.A;
#2
#2
#1 force dut.reg_file_.reg_gp_we=0;
#1 force dut.reg_file_.reg_gp_we=0;
   force dut.z80_top_ifc_n.fpga_reset=1;
   force dut.z80_top_ifc_n.fpga_reset=1;
Line 2618... Line 2632...
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
 
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.db=0;
   force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
#2 release dut.ir_.ctl_ir_we;
   release dut.ir_.db;
   release dut.ir_.db;
$fdisplay(f,"Testing opcode 6e      LD L,(HL)");
$fdisplay(f,"Testing opcode 6e      LD L,(HL)");
Line 2758... Line 2773...
   ram.Mem[41321] = 8'h50;
   ram.Mem[41321] = 8'h50;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.address_latch_.Q=16'h0000;
   force dut.address_latch_.Q=16'h0000;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_file_.reg_gp_we;
   release dut.reg_file_.reg_gp_we;
#3
#2 // Execute: M1/T1 start
   release dut.address_latch_.Q;
#1 release dut.address_latch_.Q;
#1
#1
#12 // Execute
#12 // Wait for opcode end
   force dut.reg_control_.ctl_reg_sys_we=0;
   force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2 pc=z.A;
#2
#2
#1 force dut.reg_file_.reg_gp_we=0;
#1 force dut.reg_file_.reg_gp_we=0;
   force dut.z80_top_ifc_n.fpga_reset=1;
   force dut.z80_top_ifc_n.fpga_reset=1;
Line 2792... Line 2807...
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
 
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.db=0;
   force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
#2 release dut.ir_.ctl_ir_we;
   release dut.ir_.db;
   release dut.ir_.db;
$fdisplay(f,"Testing opcode e3      EX (SP),HL");
$fdisplay(f,"Testing opcode e3      EX (SP),HL");
Line 2933... Line 2949...
   ram.Mem[884] = 8'he1;
   ram.Mem[884] = 8'he1;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.address_latch_.Q=16'h0000;
   force dut.address_latch_.Q=16'h0000;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_file_.reg_gp_we;
   release dut.reg_file_.reg_gp_we;
#3
#2 // Execute: M1/T1 start
   release dut.address_latch_.Q;
#1 release dut.address_latch_.Q;
#1
#1
#36 // Execute
#36 // Wait for opcode end
   force dut.reg_control_.ctl_reg_sys_we=0;
   force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2 pc=z.A;
#2
#2
#1 force dut.reg_file_.reg_gp_we=0;
#1 force dut.reg_file_.reg_gp_we=0;
   force dut.z80_top_ifc_n.fpga_reset=1;
   force dut.z80_top_ifc_n.fpga_reset=1;
Line 2969... Line 2985...
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
   if (ram.Mem[883]!==8'h22) $fdisplay(f,"* Mem[373]=%h !=22",ram.Mem[883]);
   if (ram.Mem[883]!==8'h22) $fdisplay(f,"* Mem[373]=%h !=22",ram.Mem[883]);
   if (ram.Mem[884]!==8'h4d) $fdisplay(f,"* Mem[374]=%h !=4d",ram.Mem[884]);
   if (ram.Mem[884]!==8'h4d) $fdisplay(f,"* Mem[374]=%h !=4d",ram.Mem[884]);
//--------------------------------------------------------------------------------
#1 // End opcode
 
 
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.db=0;
   force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
#2 release dut.ir_.ctl_ir_we;
   release dut.ir_.db;
   release dut.ir_.db;
$fdisplay(f,"Testing opcode 03      INC BC");
$fdisplay(f,"Testing opcode 03      INC BC");
Line 3107... Line 3124...
   ram.Mem[0] = 8'h03;
   ram.Mem[0] = 8'h03;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.address_latch_.Q=16'h0000;
   force dut.address_latch_.Q=16'h0000;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_file_.reg_gp_we;
   release dut.reg_file_.reg_gp_we;
#3
#2 // Execute: M1/T1 start
   release dut.address_latch_.Q;
#1 release dut.address_latch_.Q;
#1
#1
#10 // Execute
#10 // Wait for opcode end
   force dut.reg_control_.ctl_reg_sys_we=0;
   force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2 pc=z.A;
#2
#2
#1 force dut.reg_file_.reg_gp_we=0;
#1 force dut.reg_file_.reg_gp_we=0;
   force dut.z80_top_ifc_n.fpga_reset=1;
   force dut.z80_top_ifc_n.fpga_reset=1;
Line 3141... Line 3158...
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
 
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.db=0;
   force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
#2 release dut.ir_.ctl_ir_we;
   release dut.ir_.db;
   release dut.ir_.db;
$fdisplay(f,"Testing opcode 3b      DEC SP");
$fdisplay(f,"Testing opcode 3b      DEC SP");
Line 3279... Line 3297...
   ram.Mem[0] = 8'h3b;
   ram.Mem[0] = 8'h3b;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.address_latch_.Q=16'h0000;
   force dut.address_latch_.Q=16'h0000;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_file_.reg_gp_we;
   release dut.reg_file_.reg_gp_we;
#3
#2 // Execute: M1/T1 start
   release dut.address_latch_.Q;
#1 release dut.address_latch_.Q;
#1
#1
#10 // Execute
#10 // Wait for opcode end
   force dut.reg_control_.ctl_reg_sys_we=0;
   force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2 pc=z.A;
#2
#2
#1 force dut.reg_file_.reg_gp_we=0;
#1 force dut.reg_file_.reg_gp_we=0;
   force dut.z80_top_ifc_n.fpga_reset=1;
   force dut.z80_top_ifc_n.fpga_reset=1;
Line 3313... Line 3331...
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h35) $fdisplay(f,"* Reg sp p=%h !=35",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h35) $fdisplay(f,"* Reg sp p=%h !=35",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h9d) $fdisplay(f,"* Reg sp s=%h !=9d",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h9d) $fdisplay(f,"* Reg sp s=%h !=9d",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
 
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.db=0;
   force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
#2 release dut.ir_.ctl_ir_we;
   release dut.ir_.db;
   release dut.ir_.db;
$fdisplay(f,"Testing opcode 07      RLCA");
$fdisplay(f,"Testing opcode 07      RLCA");
Line 3451... Line 3470...
   ram.Mem[0] = 8'h07;
   ram.Mem[0] = 8'h07;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.address_latch_.Q=16'h0000;
   force dut.address_latch_.Q=16'h0000;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_file_.reg_gp_we;
   release dut.reg_file_.reg_gp_we;
#3
#2 // Execute: M1/T1 start
   release dut.address_latch_.Q;
#1 release dut.address_latch_.Q;
#1
#1
#6 // Execute
#6 // Wait for opcode end
   force dut.reg_control_.ctl_reg_sys_we=0;
   force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2 pc=z.A;
#2
#2
#1 force dut.reg_file_.reg_gp_we=0;
#1 force dut.reg_file_.reg_gp_we=0;
   force dut.z80_top_ifc_n.fpga_reset=1;
   force dut.z80_top_ifc_n.fpga_reset=1;
Line 3485... Line 3504...
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
 
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.db=0;
   force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
#2 release dut.ir_.ctl_ir_we;
   release dut.ir_.db;
   release dut.ir_.db;
$fdisplay(f,"Testing opcode 1f      RRA");
$fdisplay(f,"Testing opcode 1f      RRA");
Line 3623... Line 3643...
   ram.Mem[0] = 8'h1f;
   ram.Mem[0] = 8'h1f;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.address_latch_.Q=16'h0000;
   force dut.address_latch_.Q=16'h0000;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_file_.reg_gp_we;
   release dut.reg_file_.reg_gp_we;
#3
#2 // Execute: M1/T1 start
   release dut.address_latch_.Q;
#1 release dut.address_latch_.Q;
#1
#1
#6 // Execute
#6 // Wait for opcode end
   force dut.reg_control_.ctl_reg_sys_we=0;
   force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2 pc=z.A;
#2
#2
#1 force dut.reg_file_.reg_gp_we=0;
#1 force dut.reg_file_.reg_gp_we=0;
   force dut.z80_top_ifc_n.fpga_reset=1;
   force dut.z80_top_ifc_n.fpga_reset=1;
Line 3657... Line 3677...
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
 
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.db=0;
   force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
#2 release dut.ir_.ctl_ir_we;
   release dut.ir_.db;
   release dut.ir_.db;
$fdisplay(f,"Testing opcode cb09    RRC C");
$fdisplay(f,"Testing opcode cb09    RRC C");
Line 3798... Line 3819...
   ram.Mem[22982] = 8'h9e;
   ram.Mem[22982] = 8'h9e;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.address_latch_.Q=16'h0000;
   force dut.address_latch_.Q=16'h0000;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_file_.reg_gp_we;
   release dut.reg_file_.reg_gp_we;
#3
#2 // Execute: M1/T1 start
   release dut.address_latch_.Q;
#1 release dut.address_latch_.Q;
#1
#1
#14 // Execute
#14 // Wait for opcode end
   force dut.reg_control_.ctl_reg_sys_we=0;
   force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2 pc=z.A;
#2
#2
#1 force dut.reg_file_.reg_gp_we=0;
#1 force dut.reg_file_.reg_gp_we=0;
   force dut.z80_top_ifc_n.fpga_reset=1;
   force dut.z80_top_ifc_n.fpga_reset=1;
Line 3832... Line 3853...
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
 
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.db=0;
   force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
#2 release dut.ir_.ctl_ir_we;
   release dut.ir_.db;
   release dut.ir_.db;
$fdisplay(f,"Testing opcode cb11    RL C");
$fdisplay(f,"Testing opcode cb11    RL C");
Line 3973... Line 3995...
   ram.Mem[60738] = 8'hb7;
   ram.Mem[60738] = 8'hb7;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.address_latch_.Q=16'h0000;
   force dut.address_latch_.Q=16'h0000;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_file_.reg_gp_we;
   release dut.reg_file_.reg_gp_we;
#3
#2 // Execute: M1/T1 start
   release dut.address_latch_.Q;
#1 release dut.address_latch_.Q;
#1
#1
#14 // Execute
#14 // Wait for opcode end
   force dut.reg_control_.ctl_reg_sys_we=0;
   force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2 pc=z.A;
#2
#2
#1 force dut.reg_file_.reg_gp_we=0;
#1 force dut.reg_file_.reg_gp_we=0;
   force dut.z80_top_ifc_n.fpga_reset=1;
   force dut.z80_top_ifc_n.fpga_reset=1;
Line 4007... Line 4029...
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
 
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.db=0;
   force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
#2 release dut.ir_.ctl_ir_we;
   release dut.ir_.db;
   release dut.ir_.db;
$fdisplay(f,"Testing opcode cb36    SLL (HL)*");
$fdisplay(f,"Testing opcode cb36    SLL (HL)*");
Line 4148... Line 4171...
   ram.Mem[27960] = 8'hf1;
   ram.Mem[27960] = 8'hf1;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.address_latch_.Q=16'h0000;
   force dut.address_latch_.Q=16'h0000;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_file_.reg_gp_we;
   release dut.reg_file_.reg_gp_we;
#3
#2 // Execute: M1/T1 start
   release dut.address_latch_.Q;
#1 release dut.address_latch_.Q;
#1
#1
#28 // Execute
#28 // Wait for opcode end
   force dut.reg_control_.ctl_reg_sys_we=0;
   force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2 pc=z.A;
#2
#2
#1 force dut.reg_file_.reg_gp_we=0;
#1 force dut.reg_file_.reg_gp_we=0;
   force dut.z80_top_ifc_n.fpga_reset=1;
   force dut.z80_top_ifc_n.fpga_reset=1;
Line 4183... Line 4206...
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
   if (ram.Mem[27960]!==8'he3) $fdisplay(f,"* Mem[6d38]=%h !=e3",ram.Mem[27960]);
   if (ram.Mem[27960]!==8'he3) $fdisplay(f,"* Mem[6d38]=%h !=e3",ram.Mem[27960]);
//--------------------------------------------------------------------------------
#1 // End opcode
 
 
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.db=0;
   force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
#2 release dut.ir_.ctl_ir_we;
   release dut.ir_.db;
   release dut.ir_.db;
$fdisplay(f,"Testing opcode cb52    BIT 2,D");
$fdisplay(f,"Testing opcode cb52    BIT 2,D");
Line 4324... Line 4348...
   ram.Mem[44100] = 8'h00;
   ram.Mem[44100] = 8'h00;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.address_latch_.Q=16'h0000;
   force dut.address_latch_.Q=16'h0000;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_file_.reg_gp_we;
   release dut.reg_file_.reg_gp_we;
#3
#2 // Execute: M1/T1 start
   release dut.address_latch_.Q;
#1 release dut.address_latch_.Q;
#1
#1
#14 // Execute
#14 // Wait for opcode end
   force dut.reg_control_.ctl_reg_sys_we=0;
   force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2 pc=z.A;
#2
#2
#1 force dut.reg_file_.reg_gp_we=0;
#1 force dut.reg_file_.reg_gp_we=0;
   force dut.z80_top_ifc_n.fpga_reset=1;
   force dut.z80_top_ifc_n.fpga_reset=1;
Line 4358... Line 4382...
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
 
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.db=0;
   force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
#2 release dut.ir_.ctl_ir_we;
   release dut.ir_.db;
   release dut.ir_.db;
$fdisplay(f,"Testing opcode cb93    RES 2,E");
$fdisplay(f,"Testing opcode cb93    RES 2,E");
Line 4499... Line 4524...
   ram.Mem[8756] = 8'ha0;
   ram.Mem[8756] = 8'ha0;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.address_latch_.Q=16'h0000;
   force dut.address_latch_.Q=16'h0000;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_file_.reg_gp_we;
   release dut.reg_file_.reg_gp_we;
#3
#2 // Execute: M1/T1 start
   release dut.address_latch_.Q;
#1 release dut.address_latch_.Q;
#1
#1
#14 // Execute
#14 // Wait for opcode end
   force dut.reg_control_.ctl_reg_sys_we=0;
   force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2 pc=z.A;
#2
#2
#1 force dut.reg_file_.reg_gp_we=0;
#1 force dut.reg_file_.reg_gp_we=0;
   force dut.z80_top_ifc_n.fpga_reset=1;
   force dut.z80_top_ifc_n.fpga_reset=1;
Line 4533... Line 4558...
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
 
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.db=0;
   force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
#2 release dut.ir_.ctl_ir_we;
   release dut.ir_.db;
   release dut.ir_.db;
$fdisplay(f,"Testing opcode cbc4    SET 0,H");
$fdisplay(f,"Testing opcode cbc4    SET 0,H");
Line 4674... Line 4700...
   ram.Mem[22646] = 8'h9d;
   ram.Mem[22646] = 8'h9d;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.address_latch_.Q=16'h0000;
   force dut.address_latch_.Q=16'h0000;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_file_.reg_gp_we;
   release dut.reg_file_.reg_gp_we;
#3
#2 // Execute: M1/T1 start
   release dut.address_latch_.Q;
#1 release dut.address_latch_.Q;
#1
#1
#14 // Execute
#14 // Wait for opcode end
   force dut.reg_control_.ctl_reg_sys_we=0;
   force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2 pc=z.A;
#2
#2
#1 force dut.reg_file_.reg_gp_we=0;
#1 force dut.reg_file_.reg_gp_we=0;
   force dut.z80_top_ifc_n.fpga_reset=1;
   force dut.z80_top_ifc_n.fpga_reset=1;
Line 4708... Line 4734...
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
 
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.db=0;
   force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
#2 release dut.ir_.ctl_ir_we;
   release dut.ir_.db;
   release dut.ir_.db;
$fdisplay(f,"Testing opcode dd75    LD (IX+d),L");
$fdisplay(f,"Testing opcode dd75    LD (IX+d),L");
Line 4848... Line 4875...
   ram.Mem[2] = 8'h30;
   ram.Mem[2] = 8'h30;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.address_latch_.Q=16'h0000;
   force dut.address_latch_.Q=16'h0000;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_file_.reg_gp_we;
   release dut.reg_file_.reg_gp_we;
#3
#2 // Execute: M1/T1 start
   release dut.address_latch_.Q;
#1 release dut.address_latch_.Q;
#1
#1
#36 // Execute
#36 // Wait for opcode end
   force dut.reg_control_.ctl_reg_sys_we=0;
   force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2 pc=z.A;
#2
#2
#1 force dut.reg_file_.reg_gp_we=0;
#1 force dut.reg_file_.reg_gp_we=0;
   force dut.z80_top_ifc_n.fpga_reset=1;
   force dut.z80_top_ifc_n.fpga_reset=1;
Line 4883... Line 4910...
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (pc!==16'h0003) $fdisplay(f,"* PC=%h !=0003",pc);
   if (pc!==16'h0003) $fdisplay(f,"* PC=%h !=0003",pc);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
   if (ram.Mem[44668]!==8'h4f) $fdisplay(f,"* Mem[ae7c]=%h !=4f",ram.Mem[44668]);
   if (ram.Mem[44668]!==8'h4f) $fdisplay(f,"* Mem[ae7c]=%h !=4f",ram.Mem[44668]);
//--------------------------------------------------------------------------------
#1 // End opcode
 
 
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.ctl_ir_we=1;
   force dut.ir_.db=0;
   force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
#2 release dut.ir_.ctl_ir_we;
   release dut.ir_.db;
   release dut.ir_.db;
$fdisplay(f,"Testing opcode dd4e    LD C,(IX+d)");
$fdisplay(f,"Testing opcode dd4e    LD C,(IX+d)");
Line 5025... Line 5053...
   ram.Mem[55673] = 8'h76;
   ram.Mem[55673] = 8'h76;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.z80_top_ifc_n.fpga_reset=0;
   force dut.address_latch_.Q=16'h0000;
   force dut.address_latch_.Q=16'h0000;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_control_.ctl_reg_sys_we;
   release dut.reg_file_.reg_gp_we;
   release dut.reg_file_.reg_gp_we;
#3
#2 // Execute: M1/T1 start
   release dut.address_latch_.Q;
#1 release dut.address_latch_.Q;
#1
#1
#36 // Execute
#36 // Wait for opcode end
   force dut.reg_control_.ctl_reg_sys_we=0;
   force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2 pc=z.A;
#2
#2
#1 force dut.reg_file_.reg_gp_we=0;
#1 force dut.reg_file_.reg_gp_we=0;
   force dut.z80_top_ifc_n.fpga_reset=1;
   force dut.z80_top_ifc_n.fpga_reset=1;
Line 5059... Line 5087...
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
   if (pc!==16'h0003) $fdisplay(f,"* PC=%h !=0003",pc);
   if (pc!==16'h0003) $fdisplay(f,"* PC=%h !=0003",pc);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
`define TOTAL_CLKS 1559
 
 
`define TOTAL_CLKS 1588
$fdisplay(f,"=== Tests completed ===");
$fdisplay(f,"=== Tests completed ===");
 
 
 No newline at end of file
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.