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URL https://opencores.org/ocsvn/a-z80/a-z80/trunk

Subversion Repositories a-z80

[/] [a-z80/] [trunk/] [cpu/] [toplevel/] [test_fuse.vh] - Diff between revs 6 and 8

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Rev 6 Rev 8
Line 1... Line 1... 
// Automatically generated by genfuse.py
 
// Automatically generated by genfuse.py
 
 
 
 
 
 
 
force dut.resets_.clrpc=0;
 
force dut.reg_file_.reg_gp_we=0;
 
force dut.reg_file_.reg_gp_we=0;
 
force dut.reg_control_.ctl_reg_sys_we=0;
 
force dut.reg_control_.ctl_reg_sys_we=0;
 
force dut.z80_top_ifc_n.fpga_reset=1;
 
force dut.z80_top_ifc_n.fpga_reset=1;
 
#2
 
#2
 
//--------------------------------------------------------------------------------
 
//--------------------------------------------------------------------------------
 
   force dut.instruction_reg_.ctl_ir_we=1;
 
   force dut.ir_.ctl_ir_we=1;
 
   force dut.instruction_reg_.db=0;
 
   force dut.ir_.db=0;
 
#2 release dut.instruction_reg_.ctl_ir_we;
 
#2 release dut.ir_.ctl_ir_we;
 
   release dut.instruction_reg_.db;
 
   release dut.ir_.db;
 
$fdisplay(f,"Testing opcode 00      NOP");
 
$fdisplay(f,"Testing opcode 00      NOP");
 
   // Preset af
 
   // Preset af
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
Line 137... Line 138... 
   release dut.reg_file_.b2v_latch_ir_lo.db;
 
   release dut.reg_file_.b2v_latch_ir_lo.db;
 
   release dut.reg_file_.b2v_latch_ir_hi.db;
 
   release dut.reg_file_.b2v_latch_ir_hi.db;
 
   // Preset memory
 
   // Preset memory
 
   ram.Mem[0] = 8'h00;
 
   ram.Mem[0] = 8'h00;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.address_latch_.abus=16'h0000;
 
   force dut.address_latch_.Q=16'h0000;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_file_.reg_gp_we;
 
   release dut.reg_file_.reg_gp_we;
 
#3
 
#3
 
   release dut.address_latch_.abus;
 
   release dut.address_latch_.Q;
 
#1
 
#1
 
#6 // Execute
 
#6 // Execute
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
#2 pc=z.A;
 
#2 pc=z.A;
 
#2
 
#2
Line 175... Line 176... 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
 
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
//--------------------------------------------------------------------------------
 
//--------------------------------------------------------------------------------
 
   force dut.instruction_reg_.ctl_ir_we=1;
 
   force dut.ir_.ctl_ir_we=1;
 
   force dut.instruction_reg_.db=0;
 
   force dut.ir_.db=0;
 
#2 release dut.instruction_reg_.ctl_ir_we;
 
#2 release dut.ir_.ctl_ir_we;
 
   release dut.instruction_reg_.db;
 
   release dut.ir_.db;
 
$fdisplay(f,"Testing opcode ed67    RRD");
 
$fdisplay(f,"Testing opcode ed67    RRD");
 
   // Preset af
 
   // Preset af
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h24;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h24;
Line 312... Line 313... 
   ram.Mem[0] = 8'hed;
 
   ram.Mem[0] = 8'hed;
 
   ram.Mem[1] = 8'h67;
 
   ram.Mem[1] = 8'h67;
 
   // Preset memory
 
   // Preset memory
 
   ram.Mem[47582] = 8'h93;
 
   ram.Mem[47582] = 8'h93;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.address_latch_.abus=16'h0000;
 
   force dut.address_latch_.Q=16'h0000;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_file_.reg_gp_we;
 
   release dut.reg_file_.reg_gp_we;
 
#3
 
#3
 
   release dut.address_latch_.abus;
 
   release dut.address_latch_.Q;
 
#1
 
#1
 
#34 // Execute
 
#34 // Execute
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
#2 pc=z.A;
 
#2 pc=z.A;
 
#2
 
#2
Line 351... Line 352... 
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
 
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
   if (ram.Mem[47582]!==8'h69) $fdisplay(f,"* Mem[b9de]=%h !=69",ram.Mem[47582]);
 
   if (ram.Mem[47582]!==8'h69) $fdisplay(f,"* Mem[b9de]=%h !=69",ram.Mem[47582]);
 
//--------------------------------------------------------------------------------
 
//--------------------------------------------------------------------------------
 
   force dut.instruction_reg_.ctl_ir_we=1;
 
   force dut.ir_.ctl_ir_we=1;
 
   force dut.instruction_reg_.db=0;
 
   force dut.ir_.db=0;
 
#2 release dut.instruction_reg_.ctl_ir_we;
 
#2 release dut.ir_.ctl_ir_we;
 
   release dut.instruction_reg_.db;
 
   release dut.ir_.db;
 
$fdisplay(f,"Testing opcode ed6f    RLD");
 
$fdisplay(f,"Testing opcode ed6f    RLD");
 
   // Preset af
 
   // Preset af
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h8b;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h8b;
Line 488... Line 489... 
   ram.Mem[0] = 8'hed;
 
   ram.Mem[0] = 8'hed;
 
   ram.Mem[1] = 8'h6f;
 
   ram.Mem[1] = 8'h6f;
 
   // Preset memory
 
   // Preset memory
 
   ram.Mem[16444] = 8'hc4;
 
   ram.Mem[16444] = 8'hc4;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.address_latch_.abus=16'h0000;
 
   force dut.address_latch_.Q=16'h0000;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_file_.reg_gp_we;
 
   release dut.reg_file_.reg_gp_we;
 
#3
 
#3
 
   release dut.address_latch_.abus;
 
   release dut.address_latch_.Q;
 
#1
 
#1
 
#34 // Execute
 
#34 // Execute
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
#2 pc=z.A;
 
#2 pc=z.A;
 
#2
 
#2
Line 527... Line 528... 
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
 
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
   if (ram.Mem[16444]!==8'h45) $fdisplay(f,"* Mem[403c]=%h !=45",ram.Mem[16444]);
 
   if (ram.Mem[16444]!==8'h45) $fdisplay(f,"* Mem[403c]=%h !=45",ram.Mem[16444]);
 
//--------------------------------------------------------------------------------
 
//--------------------------------------------------------------------------------
 
   force dut.instruction_reg_.ctl_ir_we=1;
 
   force dut.ir_.ctl_ir_we=1;
 
   force dut.instruction_reg_.db=0;
 
   force dut.ir_.db=0;
 
#2 release dut.instruction_reg_.ctl_ir_we;
 
#2 release dut.ir_.ctl_ir_we;
 
   release dut.instruction_reg_.db;
 
   release dut.ir_.db;
 
$fdisplay(f,"Testing opcode 81      ADD A,C");
 
$fdisplay(f,"Testing opcode 81      ADD A,C");
 
   // Preset af
 
   // Preset af
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
Line 663... Line 664... 
   // Preset memory
 
   // Preset memory
 
   ram.Mem[0] = 8'h81;
 
   ram.Mem[0] = 8'h81;
 
   // Preset memory
 
   // Preset memory
 
   ram.Mem[56486] = 8'h49;
 
   ram.Mem[56486] = 8'h49;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.address_latch_.abus=16'h0000;
 
   force dut.address_latch_.Q=16'h0000;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_file_.reg_gp_we;
 
   release dut.reg_file_.reg_gp_we;
 
#3
 
#3
 
   release dut.address_latch_.abus;
 
   release dut.address_latch_.Q;
 
#1
 
#1
 
#6 // Execute
 
#6 // Execute
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
#2 pc=z.A;
 
#2 pc=z.A;
 
#2
 
#2
Line 701... Line 702... 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
 
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
//--------------------------------------------------------------------------------
 
//--------------------------------------------------------------------------------
 
   force dut.instruction_reg_.ctl_ir_we=1;
 
   force dut.ir_.ctl_ir_we=1;
 
   force dut.instruction_reg_.db=0;
 
   force dut.ir_.db=0;
 
#2 release dut.instruction_reg_.ctl_ir_we;
 
#2 release dut.ir_.ctl_ir_we;
 
   release dut.instruction_reg_.db;
 
   release dut.ir_.db;
 
$fdisplay(f,"Testing opcode cb41    BIT 0,C");
 
$fdisplay(f,"Testing opcode cb41    BIT 0,C");
 
   // Preset af
 
   // Preset af
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
Line 838... Line 839... 
   ram.Mem[0] = 8'hcb;
 
   ram.Mem[0] = 8'hcb;
 
   ram.Mem[1] = 8'h41;
 
   ram.Mem[1] = 8'h41;
 
   // Preset memory
 
   // Preset memory
 
   ram.Mem[31721] = 8'hf7;
 
   ram.Mem[31721] = 8'hf7;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.address_latch_.abus=16'h0000;
 
   force dut.address_latch_.Q=16'h0000;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_file_.reg_gp_we;
 
   release dut.reg_file_.reg_gp_we;
 
#3
 
#3
 
   release dut.address_latch_.abus;
 
   release dut.address_latch_.Q;
 
#1
 
#1
 
#14 // Execute
 
#14 // Execute
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
#2 pc=z.A;
 
#2 pc=z.A;
 
#2
 
#2
Line 876... Line 877... 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
 
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
//--------------------------------------------------------------------------------
 
//--------------------------------------------------------------------------------
 
   force dut.instruction_reg_.ctl_ir_we=1;
 
   force dut.ir_.ctl_ir_we=1;
 
   force dut.instruction_reg_.db=0;
 
   force dut.ir_.db=0;
 
#2 release dut.instruction_reg_.ctl_ir_we;
 
#2 release dut.ir_.ctl_ir_we;
 
   release dut.instruction_reg_.db;
 
   release dut.ir_.db;
 
$fdisplay(f,"Testing opcode cb93    RES 2,E");
 
$fdisplay(f,"Testing opcode cb93    RES 2,E");
 
   // Preset af
 
   // Preset af
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
Line 1013... Line 1014... 
   ram.Mem[0] = 8'hcb;
 
   ram.Mem[0] = 8'hcb;
 
   ram.Mem[1] = 8'h93;
 
   ram.Mem[1] = 8'h93;
 
   // Preset memory
 
   // Preset memory
 
   ram.Mem[8756] = 8'ha0;
 
   ram.Mem[8756] = 8'ha0;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.address_latch_.abus=16'h0000;
 
   force dut.address_latch_.Q=16'h0000;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_file_.reg_gp_we;
 
   release dut.reg_file_.reg_gp_we;
 
#3
 
#3
 
   release dut.address_latch_.abus;
 
   release dut.address_latch_.Q;
 
#1
 
#1
 
#14 // Execute
 
#14 // Execute
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
#2 pc=z.A;
 
#2 pc=z.A;
 
#2
 
#2
Line 1051... Line 1052... 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
 
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
//--------------------------------------------------------------------------------
 
//--------------------------------------------------------------------------------
 
   force dut.instruction_reg_.ctl_ir_we=1;
 
   force dut.ir_.ctl_ir_we=1;
 
   force dut.instruction_reg_.db=0;
 
   force dut.ir_.db=0;
 
#2 release dut.instruction_reg_.ctl_ir_we;
 
#2 release dut.ir_.ctl_ir_we;
 
   release dut.instruction_reg_.db;
 
   release dut.ir_.db;
 
$fdisplay(f,"Testing opcode cbe5    SET 4,L");
 
$fdisplay(f,"Testing opcode cbe5    SET 4,L");
 
   // Preset af
 
   // Preset af
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
Line 1188... Line 1189... 
   ram.Mem[0] = 8'hcb;
 
   ram.Mem[0] = 8'hcb;
 
   ram.Mem[1] = 8'he5;
 
   ram.Mem[1] = 8'he5;
 
   // Preset memory
 
   // Preset memory
 
   ram.Mem[46223] = 8'hcf;
 
   ram.Mem[46223] = 8'hcf;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.address_latch_.abus=16'h0000;
 
   force dut.address_latch_.Q=16'h0000;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_file_.reg_gp_we;
 
   release dut.reg_file_.reg_gp_we;
 
#3
 
#3
 
   release dut.address_latch_.abus;
 
   release dut.address_latch_.Q;
 
#1
 
#1
 
#14 // Execute
 
#14 // Execute
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
#2 pc=z.A;
 
#2 pc=z.A;
 
#2
 
#2
Line 1226... Line 1227... 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
 
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
//--------------------------------------------------------------------------------
 
//--------------------------------------------------------------------------------
 
   force dut.instruction_reg_.ctl_ir_we=1;
 
   force dut.ir_.ctl_ir_we=1;
 
   force dut.instruction_reg_.db=0;
 
   force dut.ir_.db=0;
 
#2 release dut.instruction_reg_.ctl_ir_we;
 
#2 release dut.ir_.ctl_ir_we;
 
   release dut.instruction_reg_.db;
 
   release dut.ir_.db;
 
$fdisplay(f,"Testing opcode 8c      ADC A,H");
 
$fdisplay(f,"Testing opcode 8c      ADC A,H");
 
   // Preset af
 
   // Preset af
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
Line 1362... Line 1363... 
   // Preset memory
 
   // Preset memory
 
   ram.Mem[0] = 8'h8c;
 
   ram.Mem[0] = 8'h8c;
 
   // Preset memory
 
   // Preset memory
 
   ram.Mem[56486] = 8'h49;
 
   ram.Mem[56486] = 8'h49;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.address_latch_.abus=16'h0000;
 
   force dut.address_latch_.Q=16'h0000;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_file_.reg_gp_we;
 
   release dut.reg_file_.reg_gp_we;
 
#3
 
#3
 
   release dut.address_latch_.abus;
 
   release dut.address_latch_.Q;
 
#1
 
#1
 
#6 // Execute
 
#6 // Execute
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
#2 pc=z.A;
 
#2 pc=z.A;
 
#2
 
#2
Line 1400... Line 1401... 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
 
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
//--------------------------------------------------------------------------------
 
//--------------------------------------------------------------------------------
 
   force dut.instruction_reg_.ctl_ir_we=1;
 
   force dut.ir_.ctl_ir_we=1;
 
   force dut.instruction_reg_.db=0;
 
   force dut.ir_.db=0;
 
#2 release dut.instruction_reg_.ctl_ir_we;
 
#2 release dut.ir_.ctl_ir_we;
 
   release dut.instruction_reg_.db;
 
   release dut.ir_.db;
 
$fdisplay(f,"Testing opcode 92      SUB D");
 
$fdisplay(f,"Testing opcode 92      SUB D");
 
   // Preset af
 
   // Preset af
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
Line 1536... Line 1537... 
   // Preset memory
 
   // Preset memory
 
   ram.Mem[0] = 8'h92;
 
   ram.Mem[0] = 8'h92;
 
   // Preset memory
 
   // Preset memory
 
   ram.Mem[56486] = 8'h49;
 
   ram.Mem[56486] = 8'h49;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.address_latch_.abus=16'h0000;
 
   force dut.address_latch_.Q=16'h0000;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_file_.reg_gp_we;
 
   release dut.reg_file_.reg_gp_we;
 
#3
 
#3
 
   release dut.address_latch_.abus;
 
   release dut.address_latch_.Q;
 
#1
 
#1
 
#6 // Execute
 
#6 // Execute
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
#2 pc=z.A;
 
#2 pc=z.A;
 
#2
 
#2
Line 1574... Line 1575... 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
 
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
//--------------------------------------------------------------------------------
 
//--------------------------------------------------------------------------------
 
   force dut.instruction_reg_.ctl_ir_we=1;
 
   force dut.ir_.ctl_ir_we=1;
 
   force dut.instruction_reg_.db=0;
 
   force dut.ir_.db=0;
 
#2 release dut.instruction_reg_.ctl_ir_we;
 
#2 release dut.ir_.ctl_ir_we;
 
   release dut.instruction_reg_.db;
 
   release dut.ir_.db;
 
$fdisplay(f,"Testing opcode 9d      SBC A,L");
 
$fdisplay(f,"Testing opcode 9d      SBC A,L");
 
   // Preset af
 
   // Preset af
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
Line 1710... Line 1711... 
   // Preset memory
 
   // Preset memory
 
   ram.Mem[0] = 8'h9d;
 
   ram.Mem[0] = 8'h9d;
 
   // Preset memory
 
   // Preset memory
 
   ram.Mem[56486] = 8'h49;
 
   ram.Mem[56486] = 8'h49;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.address_latch_.abus=16'h0000;
 
   force dut.address_latch_.Q=16'h0000;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_file_.reg_gp_we;
 
   release dut.reg_file_.reg_gp_we;
 
#3
 
#3
 
   release dut.address_latch_.abus;
 
   release dut.address_latch_.Q;
 
#1
 
#1
 
#6 // Execute
 
#6 // Execute
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
#2 pc=z.A;
 
#2 pc=z.A;
 
#2
 
#2
Line 1748... Line 1749... 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
 
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
//--------------------------------------------------------------------------------
 
//--------------------------------------------------------------------------------
 
   force dut.instruction_reg_.ctl_ir_we=1;
 
   force dut.ir_.ctl_ir_we=1;
 
   force dut.instruction_reg_.db=0;
 
   force dut.ir_.db=0;
 
#2 release dut.instruction_reg_.ctl_ir_we;
 
#2 release dut.ir_.ctl_ir_we;
 
   release dut.instruction_reg_.db;
 
   release dut.ir_.db;
 
$fdisplay(f,"Testing opcode a3      AND E");
 
$fdisplay(f,"Testing opcode a3      AND E");
 
   // Preset af
 
   // Preset af
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
Line 1884... Line 1885... 
   // Preset memory
 
   // Preset memory
 
   ram.Mem[0] = 8'ha3;
 
   ram.Mem[0] = 8'ha3;
 
   // Preset memory
 
   // Preset memory
 
   ram.Mem[56486] = 8'h49;
 
   ram.Mem[56486] = 8'h49;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.address_latch_.abus=16'h0000;
 
   force dut.address_latch_.Q=16'h0000;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_file_.reg_gp_we;
 
   release dut.reg_file_.reg_gp_we;
 
#3
 
#3
 
   release dut.address_latch_.abus;
 
   release dut.address_latch_.Q;
 
#1
 
#1
 
#6 // Execute
 
#6 // Execute
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
#2 pc=z.A;
 
#2 pc=z.A;
 
#2
 
#2
Line 1922... Line 1923... 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
 
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
//--------------------------------------------------------------------------------
 
//--------------------------------------------------------------------------------
 
   force dut.instruction_reg_.ctl_ir_we=1;
 
   force dut.ir_.ctl_ir_we=1;
 
   force dut.instruction_reg_.db=0;
 
   force dut.ir_.db=0;
 
#2 release dut.instruction_reg_.ctl_ir_we;
 
#2 release dut.ir_.ctl_ir_we;
 
   release dut.instruction_reg_.db;
 
   release dut.ir_.db;
 
$fdisplay(f,"Testing opcode ae      XOR (HL)");
 
$fdisplay(f,"Testing opcode ae      XOR (HL)");
 
   // Preset af
 
   // Preset af
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
Line 2058... Line 2059... 
   // Preset memory
 
   // Preset memory
 
   ram.Mem[0] = 8'hae;
 
   ram.Mem[0] = 8'hae;
 
   // Preset memory
 
   // Preset memory
 
   ram.Mem[56486] = 8'h49;
 
   ram.Mem[56486] = 8'h49;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.address_latch_.abus=16'h0000;
 
   force dut.address_latch_.Q=16'h0000;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_file_.reg_gp_we;
 
   release dut.reg_file_.reg_gp_we;
 
#3
 
#3
 
   release dut.address_latch_.abus;
 
   release dut.address_latch_.Q;
 
#1
 
#1
 
#12 // Execute
 
#12 // Execute
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
#2 pc=z.A;
 
#2 pc=z.A;
 
#2
 
#2
Line 2096... Line 2097... 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
 
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
//--------------------------------------------------------------------------------
 
//--------------------------------------------------------------------------------
 
   force dut.instruction_reg_.ctl_ir_we=1;
 
   force dut.ir_.ctl_ir_we=1;
 
   force dut.instruction_reg_.db=0;
 
   force dut.ir_.db=0;
 
#2 release dut.instruction_reg_.ctl_ir_we;
 
#2 release dut.ir_.ctl_ir_we;
 
   release dut.instruction_reg_.db;
 
   release dut.ir_.db;
 
$fdisplay(f,"Testing opcode b4      OR H");
 
$fdisplay(f,"Testing opcode b4      OR H");
 
   // Preset af
 
   // Preset af
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
Line 2232... Line 2233... 
   // Preset memory
 
   // Preset memory
 
   ram.Mem[0] = 8'hb4;
 
   ram.Mem[0] = 8'hb4;
 
   // Preset memory
 
   // Preset memory
 
   ram.Mem[56486] = 8'h49;
 
   ram.Mem[56486] = 8'h49;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.address_latch_.abus=16'h0000;
 
   force dut.address_latch_.Q=16'h0000;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_file_.reg_gp_we;
 
   release dut.reg_file_.reg_gp_we;
 
#3
 
#3
 
   release dut.address_latch_.abus;
 
   release dut.address_latch_.Q;
 
#1
 
#1
 
#6 // Execute
 
#6 // Execute
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
#2 pc=z.A;
 
#2 pc=z.A;
 
#2
 
#2
Line 2270... Line 2271... 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
 
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
//--------------------------------------------------------------------------------
 
//--------------------------------------------------------------------------------
 
   force dut.instruction_reg_.ctl_ir_we=1;
 
   force dut.ir_.ctl_ir_we=1;
 
   force dut.instruction_reg_.db=0;
 
   force dut.ir_.db=0;
 
#2 release dut.instruction_reg_.ctl_ir_we;
 
#2 release dut.ir_.ctl_ir_we;
 
   release dut.instruction_reg_.db;
 
   release dut.ir_.db;
 
$fdisplay(f,"Testing opcode bf      CP A");
 
$fdisplay(f,"Testing opcode bf      CP A");
 
   // Preset af
 
   // Preset af
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
Line 2406... Line 2407... 
   // Preset memory
 
   // Preset memory
 
   ram.Mem[0] = 8'hbf;
 
   ram.Mem[0] = 8'hbf;
 
   // Preset memory
 
   // Preset memory
 
   ram.Mem[56486] = 8'h49;
 
   ram.Mem[56486] = 8'h49;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.address_latch_.abus=16'h0000;
 
   force dut.address_latch_.Q=16'h0000;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_file_.reg_gp_we;
 
   release dut.reg_file_.reg_gp_we;
 
#3
 
#3
 
   release dut.address_latch_.abus;
 
   release dut.address_latch_.Q;
 
#1
 
#1
 
#6 // Execute
 
#6 // Execute
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
#2 pc=z.A;
 
#2 pc=z.A;
 
#2
 
#2
Line 2444... Line 2445... 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
 
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
//--------------------------------------------------------------------------------
 
//--------------------------------------------------------------------------------
 
   force dut.instruction_reg_.ctl_ir_we=1;
 
   force dut.ir_.ctl_ir_we=1;
 
   force dut.instruction_reg_.db=0;
 
   force dut.ir_.db=0;
 
#2 release dut.instruction_reg_.ctl_ir_we;
 
#2 release dut.ir_.ctl_ir_we;
 
   release dut.instruction_reg_.db;
 
   release dut.ir_.db;
 
$fdisplay(f,"Testing opcode 43      LD B,E");
 
$fdisplay(f,"Testing opcode 43      LD B,E");
 
   // Preset af
 
   // Preset af
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
Line 2580... Line 2581... 
   // Preset memory
 
   // Preset memory
 
   ram.Mem[0] = 8'h43;
 
   ram.Mem[0] = 8'h43;
 
   // Preset memory
 
   // Preset memory
 
   ram.Mem[41321] = 8'h50;
 
   ram.Mem[41321] = 8'h50;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.address_latch_.abus=16'h0000;
 
   force dut.address_latch_.Q=16'h0000;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_file_.reg_gp_we;
 
   release dut.reg_file_.reg_gp_we;
 
#3
 
#3
 
   release dut.address_latch_.abus;
 
   release dut.address_latch_.Q;
 
#1
 
#1
 
#6 // Execute
 
#6 // Execute
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
#2 pc=z.A;
 
#2 pc=z.A;
 
#2
 
#2
Line 2618... Line 2619... 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
 
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
//--------------------------------------------------------------------------------
 
//--------------------------------------------------------------------------------
 
   force dut.instruction_reg_.ctl_ir_we=1;
 
   force dut.ir_.ctl_ir_we=1;
 
   force dut.instruction_reg_.db=0;
 
   force dut.ir_.db=0;
 
#2 release dut.instruction_reg_.ctl_ir_we;
 
#2 release dut.ir_.ctl_ir_we;
 
   release dut.instruction_reg_.db;
 
   release dut.ir_.db;
 
$fdisplay(f,"Testing opcode 6e      LD L,(HL)");
 
$fdisplay(f,"Testing opcode 6e      LD L,(HL)");
 
   // Preset af
 
   // Preset af
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
Line 2754... Line 2755... 
   // Preset memory
 
   // Preset memory
 
   ram.Mem[0] = 8'h6e;
 
   ram.Mem[0] = 8'h6e;
 
   // Preset memory
 
   // Preset memory
 
   ram.Mem[41321] = 8'h50;
 
   ram.Mem[41321] = 8'h50;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.address_latch_.abus=16'h0000;
 
   force dut.address_latch_.Q=16'h0000;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_file_.reg_gp_we;
 
   release dut.reg_file_.reg_gp_we;
 
#3
 
#3
 
   release dut.address_latch_.abus;
 
   release dut.address_latch_.Q;
 
#1
 
#1
 
#12 // Execute
 
#12 // Execute
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
#2 pc=z.A;
 
#2 pc=z.A;
 
#2
 
#2
Line 2792... Line 2793... 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
 
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
//--------------------------------------------------------------------------------
 
//--------------------------------------------------------------------------------
 
   force dut.instruction_reg_.ctl_ir_we=1;
 
   force dut.ir_.ctl_ir_we=1;
 
   force dut.instruction_reg_.db=0;
 
   force dut.ir_.db=0;
 
#2 release dut.instruction_reg_.ctl_ir_we;
 
#2 release dut.ir_.ctl_ir_we;
 
   release dut.instruction_reg_.db;
 
   release dut.ir_.db;
 
$fdisplay(f,"Testing opcode e3      EX (SP),HL");
 
$fdisplay(f,"Testing opcode e3      EX (SP),HL");
 
   // Preset af
 
   // Preset af
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
Line 2929... Line 2930... 
   ram.Mem[0] = 8'he3;
 
   ram.Mem[0] = 8'he3;
 
   // Preset memory
 
   // Preset memory
 
   ram.Mem[883] = 8'h8e;
 
   ram.Mem[883] = 8'h8e;
 
   ram.Mem[884] = 8'he1;
 
   ram.Mem[884] = 8'he1;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.address_latch_.abus=16'h0000;
 
   force dut.address_latch_.Q=16'h0000;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_file_.reg_gp_we;
 
   release dut.reg_file_.reg_gp_we;
 
#3
 
#3
 
   release dut.address_latch_.abus;
 
   release dut.address_latch_.Q;
 
#1
 
#1
 
#36 // Execute
 
#36 // Execute
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
#2 pc=z.A;
 
#2 pc=z.A;
 
#2
 
#2
Line 2969... Line 2970... 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
   if (ram.Mem[883]!==8'h22) $fdisplay(f,"* Mem[373]=%h !=22",ram.Mem[883]);
 
   if (ram.Mem[883]!==8'h22) $fdisplay(f,"* Mem[373]=%h !=22",ram.Mem[883]);
 
   if (ram.Mem[884]!==8'h4d) $fdisplay(f,"* Mem[374]=%h !=4d",ram.Mem[884]);
 
   if (ram.Mem[884]!==8'h4d) $fdisplay(f,"* Mem[374]=%h !=4d",ram.Mem[884]);
 
//--------------------------------------------------------------------------------
 
//--------------------------------------------------------------------------------
 
   force dut.instruction_reg_.ctl_ir_we=1;
 
   force dut.ir_.ctl_ir_we=1;
 
   force dut.instruction_reg_.db=0;
 
   force dut.ir_.db=0;
 
#2 release dut.instruction_reg_.ctl_ir_we;
 
#2 release dut.ir_.ctl_ir_we;
 
   release dut.instruction_reg_.db;
 
   release dut.ir_.db;
 
$fdisplay(f,"Testing opcode 03      INC BC");
 
$fdisplay(f,"Testing opcode 03      INC BC");
 
   // Preset af
 
   // Preset af
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
Line 3103... Line 3104... 
   release dut.reg_file_.b2v_latch_ir_lo.db;
 
   release dut.reg_file_.b2v_latch_ir_lo.db;
 
   release dut.reg_file_.b2v_latch_ir_hi.db;
 
   release dut.reg_file_.b2v_latch_ir_hi.db;
 
   // Preset memory
 
   // Preset memory
 
   ram.Mem[0] = 8'h03;
 
   ram.Mem[0] = 8'h03;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.address_latch_.abus=16'h0000;
 
   force dut.address_latch_.Q=16'h0000;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_file_.reg_gp_we;
 
   release dut.reg_file_.reg_gp_we;
 
#3
 
#3
 
   release dut.address_latch_.abus;
 
   release dut.address_latch_.Q;
 
#1
 
#1
 
#10 // Execute
 
#10 // Execute
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
#2 pc=z.A;
 
#2 pc=z.A;
 
#2
 
#2
Line 3141... Line 3142... 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
 
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
//--------------------------------------------------------------------------------
 
//--------------------------------------------------------------------------------
 
   force dut.instruction_reg_.ctl_ir_we=1;
 
   force dut.ir_.ctl_ir_we=1;
 
   force dut.instruction_reg_.db=0;
 
   force dut.ir_.db=0;
 
#2 release dut.instruction_reg_.ctl_ir_we;
 
#2 release dut.ir_.ctl_ir_we;
 
   release dut.instruction_reg_.db;
 
   release dut.ir_.db;
 
$fdisplay(f,"Testing opcode 3b      DEC SP");
 
$fdisplay(f,"Testing opcode 3b      DEC SP");
 
   // Preset af
 
   // Preset af
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
Line 3275... Line 3276... 
   release dut.reg_file_.b2v_latch_ir_lo.db;
 
   release dut.reg_file_.b2v_latch_ir_lo.db;
 
   release dut.reg_file_.b2v_latch_ir_hi.db;
 
   release dut.reg_file_.b2v_latch_ir_hi.db;
 
   // Preset memory
 
   // Preset memory
 
   ram.Mem[0] = 8'h3b;
 
   ram.Mem[0] = 8'h3b;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.address_latch_.abus=16'h0000;
 
   force dut.address_latch_.Q=16'h0000;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_file_.reg_gp_we;
 
   release dut.reg_file_.reg_gp_we;
 
#3
 
#3
 
   release dut.address_latch_.abus;
 
   release dut.address_latch_.Q;
 
#1
 
#1
 
#10 // Execute
 
#10 // Execute
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
#2 pc=z.A;
 
#2 pc=z.A;
 
#2
 
#2
Line 3313... Line 3314... 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h9d) $fdisplay(f,"* Reg sp s=%h !=9d",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h9d) $fdisplay(f,"* Reg sp s=%h !=9d",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
 
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
//--------------------------------------------------------------------------------
 
//--------------------------------------------------------------------------------
 
   force dut.instruction_reg_.ctl_ir_we=1;
 
   force dut.ir_.ctl_ir_we=1;
 
   force dut.instruction_reg_.db=0;
 
   force dut.ir_.db=0;
 
#2 release dut.instruction_reg_.ctl_ir_we;
 
#2 release dut.ir_.ctl_ir_we;
 
   release dut.instruction_reg_.db;
 
   release dut.ir_.db;
 
$fdisplay(f,"Testing opcode 07      RLCA");
 
$fdisplay(f,"Testing opcode 07      RLCA");
 
   // Preset af
 
   // Preset af
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
Line 3447... Line 3448... 
   release dut.reg_file_.b2v_latch_ir_lo.db;
 
   release dut.reg_file_.b2v_latch_ir_lo.db;
 
   release dut.reg_file_.b2v_latch_ir_hi.db;
 
   release dut.reg_file_.b2v_latch_ir_hi.db;
 
   // Preset memory
 
   // Preset memory
 
   ram.Mem[0] = 8'h07;
 
   ram.Mem[0] = 8'h07;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.address_latch_.abus=16'h0000;
 
   force dut.address_latch_.Q=16'h0000;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_file_.reg_gp_we;
 
   release dut.reg_file_.reg_gp_we;
 
#3
 
#3
 
   release dut.address_latch_.abus;
 
   release dut.address_latch_.Q;
 
#1
 
#1
 
#6 // Execute
 
#6 // Execute
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
#2 pc=z.A;
 
#2 pc=z.A;
 
#2
 
#2
Line 3485... Line 3486... 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
 
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
//--------------------------------------------------------------------------------
 
//--------------------------------------------------------------------------------
 
   force dut.instruction_reg_.ctl_ir_we=1;
 
   force dut.ir_.ctl_ir_we=1;
 
   force dut.instruction_reg_.db=0;
 
   force dut.ir_.db=0;
 
#2 release dut.instruction_reg_.ctl_ir_we;
 
#2 release dut.ir_.ctl_ir_we;
 
   release dut.instruction_reg_.db;
 
   release dut.ir_.db;
 
$fdisplay(f,"Testing opcode 1f      RRA");
 
$fdisplay(f,"Testing opcode 1f      RRA");
 
   // Preset af
 
   // Preset af
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'hc4;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'hc4;
Line 3619... Line 3620... 
   release dut.reg_file_.b2v_latch_ir_lo.db;
 
   release dut.reg_file_.b2v_latch_ir_lo.db;
 
   release dut.reg_file_.b2v_latch_ir_hi.db;
 
   release dut.reg_file_.b2v_latch_ir_hi.db;
 
   // Preset memory
 
   // Preset memory
 
   ram.Mem[0] = 8'h1f;
 
   ram.Mem[0] = 8'h1f;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.address_latch_.abus=16'h0000;
 
   force dut.address_latch_.Q=16'h0000;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_file_.reg_gp_we;
 
   release dut.reg_file_.reg_gp_we;
 
#3
 
#3
 
   release dut.address_latch_.abus;
 
   release dut.address_latch_.Q;
 
#1
 
#1
 
#6 // Execute
 
#6 // Execute
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
#2 pc=z.A;
 
#2 pc=z.A;
 
#2
 
#2
Line 3657... Line 3658... 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
 
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
//--------------------------------------------------------------------------------
 
//--------------------------------------------------------------------------------
 
   force dut.instruction_reg_.ctl_ir_we=1;
 
   force dut.ir_.ctl_ir_we=1;
 
   force dut.instruction_reg_.db=0;
 
   force dut.ir_.db=0;
 
#2 release dut.instruction_reg_.ctl_ir_we;
 
#2 release dut.ir_.ctl_ir_we;
 
   release dut.instruction_reg_.db;
 
   release dut.ir_.db;
 
$fdisplay(f,"Testing opcode cb09    RRC C");
 
$fdisplay(f,"Testing opcode cb09    RRC C");
 
   // Preset af
 
   // Preset af
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
Line 3794... Line 3795... 
   ram.Mem[0] = 8'hcb;
 
   ram.Mem[0] = 8'hcb;
 
   ram.Mem[1] = 8'h09;
 
   ram.Mem[1] = 8'h09;
 
   // Preset memory
 
   // Preset memory
 
   ram.Mem[22982] = 8'h9e;
 
   ram.Mem[22982] = 8'h9e;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.address_latch_.abus=16'h0000;
 
   force dut.address_latch_.Q=16'h0000;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_file_.reg_gp_we;
 
   release dut.reg_file_.reg_gp_we;
 
#3
 
#3
 
   release dut.address_latch_.abus;
 
   release dut.address_latch_.Q;
 
#1
 
#1
 
#14 // Execute
 
#14 // Execute
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
#2 pc=z.A;
 
#2 pc=z.A;
 
#2
 
#2
Line 3832... Line 3833... 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
 
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
//--------------------------------------------------------------------------------
 
//--------------------------------------------------------------------------------
 
   force dut.instruction_reg_.ctl_ir_we=1;
 
   force dut.ir_.ctl_ir_we=1;
 
   force dut.instruction_reg_.db=0;
 
   force dut.ir_.db=0;
 
#2 release dut.instruction_reg_.ctl_ir_we;
 
#2 release dut.ir_.ctl_ir_we;
 
   release dut.instruction_reg_.db;
 
   release dut.ir_.db;
 
$fdisplay(f,"Testing opcode cb11    RL C");
 
$fdisplay(f,"Testing opcode cb11    RL C");
 
   // Preset af
 
   // Preset af
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
Line 3969... Line 3970... 
   ram.Mem[0] = 8'hcb;
 
   ram.Mem[0] = 8'hcb;
 
   ram.Mem[1] = 8'h11;
 
   ram.Mem[1] = 8'h11;
 
   // Preset memory
 
   // Preset memory
 
   ram.Mem[60738] = 8'hb7;
 
   ram.Mem[60738] = 8'hb7;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.address_latch_.abus=16'h0000;
 
   force dut.address_latch_.Q=16'h0000;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_file_.reg_gp_we;
 
   release dut.reg_file_.reg_gp_we;
 
#3
 
#3
 
   release dut.address_latch_.abus;
 
   release dut.address_latch_.Q;
 
#1
 
#1
 
#14 // Execute
 
#14 // Execute
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
#2 pc=z.A;
 
#2 pc=z.A;
 
#2
 
#2
Line 4007... Line 4008... 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
 
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
//--------------------------------------------------------------------------------
 
//--------------------------------------------------------------------------------
 
   force dut.instruction_reg_.ctl_ir_we=1;
 
   force dut.ir_.ctl_ir_we=1;
 
   force dut.instruction_reg_.db=0;
 
   force dut.ir_.db=0;
 
#2 release dut.instruction_reg_.ctl_ir_we;
 
#2 release dut.ir_.ctl_ir_we;
 
   release dut.instruction_reg_.db;
 
   release dut.ir_.db;
 
$fdisplay(f,"Testing opcode cb36    SLL (HL)*");
 
$fdisplay(f,"Testing opcode cb36    SLL (HL)*");
 
   // Preset af
 
   // Preset af
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
Line 4144... Line 4145... 
   ram.Mem[0] = 8'hcb;
 
   ram.Mem[0] = 8'hcb;
 
   ram.Mem[1] = 8'h36;
 
   ram.Mem[1] = 8'h36;
 
   // Preset memory
 
   // Preset memory
 
   ram.Mem[27960] = 8'hf1;
 
   ram.Mem[27960] = 8'hf1;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.address_latch_.abus=16'h0000;
 
   force dut.address_latch_.Q=16'h0000;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_file_.reg_gp_we;
 
   release dut.reg_file_.reg_gp_we;
 
#3
 
#3
 
   release dut.address_latch_.abus;
 
   release dut.address_latch_.Q;
 
#1
 
#1
 
#28 // Execute
 
#28 // Execute
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
#2 pc=z.A;
 
#2 pc=z.A;
 
#2
 
#2
Line 4183... Line 4184... 
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
 
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
   if (ram.Mem[27960]!==8'he3) $fdisplay(f,"* Mem[6d38]=%h !=e3",ram.Mem[27960]);
 
   if (ram.Mem[27960]!==8'he3) $fdisplay(f,"* Mem[6d38]=%h !=e3",ram.Mem[27960]);
 
//--------------------------------------------------------------------------------
 
//--------------------------------------------------------------------------------
 
   force dut.instruction_reg_.ctl_ir_we=1;
 
   force dut.ir_.ctl_ir_we=1;
 
   force dut.instruction_reg_.db=0;
 
   force dut.ir_.db=0;
 
#2 release dut.instruction_reg_.ctl_ir_we;
 
#2 release dut.ir_.ctl_ir_we;
 
   release dut.instruction_reg_.db;
 
   release dut.ir_.db;
 
$fdisplay(f,"Testing opcode cb52    BIT 2,D");
 
$fdisplay(f,"Testing opcode cb52    BIT 2,D");
 
   // Preset af
 
   // Preset af
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
Line 4320... Line 4321... 
   ram.Mem[0] = 8'hcb;
 
   ram.Mem[0] = 8'hcb;
 
   ram.Mem[1] = 8'h52;
 
   ram.Mem[1] = 8'h52;
 
   // Preset memory
 
   // Preset memory
 
   ram.Mem[44100] = 8'h00;
 
   ram.Mem[44100] = 8'h00;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.address_latch_.abus=16'h0000;
 
   force dut.address_latch_.Q=16'h0000;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_file_.reg_gp_we;
 
   release dut.reg_file_.reg_gp_we;
 
#3
 
#3
 
   release dut.address_latch_.abus;
 
   release dut.address_latch_.Q;
 
#1
 
#1
 
#14 // Execute
 
#14 // Execute
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
#2 pc=z.A;
 
#2 pc=z.A;
 
#2
 
#2
Line 4358... Line 4359... 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
 
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
//--------------------------------------------------------------------------------
 
//--------------------------------------------------------------------------------
 
   force dut.instruction_reg_.ctl_ir_we=1;
 
   force dut.ir_.ctl_ir_we=1;
 
   force dut.instruction_reg_.db=0;
 
   force dut.ir_.db=0;
 
#2 release dut.instruction_reg_.ctl_ir_we;
 
#2 release dut.ir_.ctl_ir_we;
 
   release dut.instruction_reg_.db;
 
   release dut.ir_.db;
 
$fdisplay(f,"Testing opcode cb93    RES 2,E");
 
$fdisplay(f,"Testing opcode cb93    RES 2,E");
 
   // Preset af
 
   // Preset af
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
Line 4495... Line 4496... 
   ram.Mem[0] = 8'hcb;
 
   ram.Mem[0] = 8'hcb;
 
   ram.Mem[1] = 8'h93;
 
   ram.Mem[1] = 8'h93;
 
   // Preset memory
 
   // Preset memory
 
   ram.Mem[8756] = 8'ha0;
 
   ram.Mem[8756] = 8'ha0;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.address_latch_.abus=16'h0000;
 
   force dut.address_latch_.Q=16'h0000;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_file_.reg_gp_we;
 
   release dut.reg_file_.reg_gp_we;
 
#3
 
#3
 
   release dut.address_latch_.abus;
 
   release dut.address_latch_.Q;
 
#1
 
#1
 
#14 // Execute
 
#14 // Execute
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
#2 pc=z.A;
 
#2 pc=z.A;
 
#2
 
#2
Line 4533... Line 4534... 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
 
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
//--------------------------------------------------------------------------------
 
//--------------------------------------------------------------------------------
 
   force dut.instruction_reg_.ctl_ir_we=1;
 
   force dut.ir_.ctl_ir_we=1;
 
   force dut.instruction_reg_.db=0;
 
   force dut.ir_.db=0;
 
#2 release dut.instruction_reg_.ctl_ir_we;
 
#2 release dut.ir_.ctl_ir_we;
 
   release dut.instruction_reg_.db;
 
   release dut.ir_.db;
 
$fdisplay(f,"Testing opcode cbc4    SET 0,H");
 
$fdisplay(f,"Testing opcode cbc4    SET 0,H");
 
   // Preset af
 
   // Preset af
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
Line 4670... Line 4671... 
   ram.Mem[0] = 8'hcb;
 
   ram.Mem[0] = 8'hcb;
 
   ram.Mem[1] = 8'hc4;
 
   ram.Mem[1] = 8'hc4;
 
   // Preset memory
 
   // Preset memory
 
   ram.Mem[22646] = 8'h9d;
 
   ram.Mem[22646] = 8'h9d;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.address_latch_.abus=16'h0000;
 
   force dut.address_latch_.Q=16'h0000;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_file_.reg_gp_we;
 
   release dut.reg_file_.reg_gp_we;
 
#3
 
#3
 
   release dut.address_latch_.abus;
 
   release dut.address_latch_.Q;
 
#1
 
#1
 
#14 // Execute
 
#14 // Execute
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
#2 pc=z.A;
 
#2 pc=z.A;
 
#2
 
#2
Line 4708... Line 4709... 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
 
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
 
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
//--------------------------------------------------------------------------------
 
//--------------------------------------------------------------------------------
 
   force dut.instruction_reg_.ctl_ir_we=1;
 
   force dut.ir_.ctl_ir_we=1;
 
   force dut.instruction_reg_.db=0;
 
   force dut.ir_.db=0;
 
#2 release dut.instruction_reg_.ctl_ir_we;
 
#2 release dut.ir_.ctl_ir_we;
 
   release dut.instruction_reg_.db;
 
   release dut.ir_.db;
 
$fdisplay(f,"Testing opcode dd75    LD (IX+d),L");
 
$fdisplay(f,"Testing opcode dd75    LD (IX+d),L");
 
   // Preset af
 
   // Preset af
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h72;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'h72;
Line 4844... Line 4845... 
   // Preset memory
 
   // Preset memory
 
   ram.Mem[0] = 8'hdd;
 
   ram.Mem[0] = 8'hdd;
 
   ram.Mem[1] = 8'h75;
 
   ram.Mem[1] = 8'h75;
 
   ram.Mem[2] = 8'h30;
 
   ram.Mem[2] = 8'h30;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.address_latch_.abus=16'h0000;
 
   force dut.address_latch_.Q=16'h0000;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_file_.reg_gp_we;
 
   release dut.reg_file_.reg_gp_we;
 
#3
 
#3
 
   release dut.address_latch_.abus;
 
   release dut.address_latch_.Q;
 
#1
 
#1
 
#36 // Execute
 
#36 // Execute
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
#2 pc=z.A;
 
#2 pc=z.A;
 
#2
 
#2
Line 4883... Line 4884... 
   if (pc!==16'h0003) $fdisplay(f,"* PC=%h !=0003",pc);
 
   if (pc!==16'h0003) $fdisplay(f,"* PC=%h !=0003",pc);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
 
   if (ram.Mem[44668]!==8'h4f) $fdisplay(f,"* Mem[ae7c]=%h !=4f",ram.Mem[44668]);
 
   if (ram.Mem[44668]!==8'h4f) $fdisplay(f,"* Mem[ae7c]=%h !=4f",ram.Mem[44668]);
 
//--------------------------------------------------------------------------------
 
//--------------------------------------------------------------------------------
 
   force dut.instruction_reg_.ctl_ir_we=1;
 
   force dut.ir_.ctl_ir_we=1;
 
   force dut.instruction_reg_.db=0;
 
   force dut.ir_.db=0;
 
#2 release dut.instruction_reg_.ctl_ir_we;
 
#2 release dut.ir_.ctl_ir_we;
 
   release dut.instruction_reg_.db;
 
   release dut.ir_.db;
 
$fdisplay(f,"Testing opcode dd4e    LD C,(IX+d)");
 
$fdisplay(f,"Testing opcode dd4e    LD C,(IX+d)");
 
   // Preset af
 
   // Preset af
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_hi.we=1;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'hf7;
 
   force dut.reg_file_.b2v_latch_af_lo.db=8'hf7;
Line 5021... Line 5022... 
   ram.Mem[1] = 8'h4e;
 
   ram.Mem[1] = 8'h4e;
 
   ram.Mem[2] = 8'h2e;
 
   ram.Mem[2] = 8'h2e;
 
   // Preset memory
 
   // Preset memory
 
   ram.Mem[55673] = 8'h76;
 
   ram.Mem[55673] = 8'h76;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.z80_top_ifc_n.fpga_reset=0;
 
   force dut.address_latch_.abus=16'h0000;
 
   force dut.address_latch_.Q=16'h0000;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_control_.ctl_reg_sys_we;
 
   release dut.reg_file_.reg_gp_we;
 
   release dut.reg_file_.reg_gp_we;
 
#3
 
#3
 
   release dut.address_latch_.abus;
 
   release dut.address_latch_.Q;
 
#1
 
#1
 
#36 // Execute
 
#36 // Execute
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
   force dut.reg_control_.ctl_reg_sys_we=0;
 
#2 pc=z.A;
 
#2 pc=z.A;
 
#2
 
#2

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