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//============================================================================
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//============================================================================
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// Implementation of the PS/2 keyboard scan-code reader
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// PS/2 keyboard scan-code reader
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//
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//
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// Copyright (C) 2014-2016 Goran Devic
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// Copyright (C) 2014-2016 Goran Devic
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//
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//
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// This program is free software; you can redistribute it and/or modify it
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License as published by the Free
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// under the terms of the GNU General Public License as published by the Free
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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//============================================================================
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//============================================================================
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module ps2_keyboard
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module ps2_keyboard
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(
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(
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input wire clk,
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input wire clk,
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input wire reset, // Reset (negative logic)
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input wire nreset, // Active low reset
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input wire PS2_CLK, // PS/2 keyboard clock line
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input wire PS2_CLK, // PS/2 keyboard clock line
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input wire PS2_DAT, // PS/2 keyboard data line
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input wire PS2_DAT, // PS/2 keyboard data line
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output wire [7:0] scan_code,// Completed keyboard scan code
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output wire [7:0] scan_code,// Completed keyboard scan code
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output reg scan_code_ready, // Active for 1 clock: scan code is ready
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output reg scan_code_ready, // Active for 1 clock: scan code is ready
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assign parity = ^shiftreg[8:0];
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assign parity = ^shiftreg[8:0];
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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// Filter the PS/2 clock signal since it might have a noise (false '1')
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// Filter the PS/2 clock signal since it might have a noise (false '1')
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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always @(posedge clk or negedge reset)
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always @(posedge clk or negedge nreset)
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begin
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begin
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if (!reset) begin
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if (!nreset) begin
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ps2_clk_in <= 1;
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ps2_clk_in <= 1;
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clk_filter <= 8'b1;
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clk_filter <= 8'b1;
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clk_edge <= 0;
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clk_edge <= 0;
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end
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end
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else begin
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else begin
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end
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end
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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// State machine to process bits of PS/2 data
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// State machine to process bits of PS/2 data
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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always @(posedge clk or negedge reset)
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always @(posedge clk or negedge nreset)
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begin
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begin
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if (!reset) begin
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if (!nreset) begin
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bit_count <= '0;
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bit_count <= '0;
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shiftreg <= '0;
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shiftreg <= '0;
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scan_code_ready <= 0;
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scan_code_ready <= 0;
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scan_code_error <= 0;
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scan_code_error <= 0;
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end
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end
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