//============================================================================
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//============================================================================
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// The implementation of the Sinclair ZX Spectrum ULA
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// Sinclair ZX Spectrum ULA
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//
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//
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// Copyright (C) 2014-2016 Goran Devic
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// Copyright (C) 2014-2016 Goran Devic
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//
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//
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// This program is free software; you can redistribute it and/or modify it
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License as published by the Free
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// under the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 of the License, or (at your option)
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// Software Foundation; either version 2 of the License, or (at your option)
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// any later version.
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// any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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// more details.
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// more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// You should have received a copy of the GNU General Public License along
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// with this program; if not, write to the Free Software Foundation, Inc.,
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// with this program; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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//============================================================================
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//============================================================================
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module ula
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module ula
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(
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(
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//-------- Clocks and reset -----------------
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//-------- Clocks and reset -----------------
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input wire CLOCK_27, // Input clock 27 MHz
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input wire CLOCK_27, // Input clock 27 MHz
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input wire CLOCK_24, // Input clock 24 MHz
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input wire CLOCK_24, // Input clock 24 MHz
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input wire turbo, // Turbo speed (3.5 MHz x 2 = 7.0 MHz)
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input wire turbo, // Turbo speed (3.5 MHz x 2 = 7.0 MHz)
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output wire clk_vram,
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output wire clk_vram,
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input wire reset, // KEY0 is reset
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input wire nreset, // Active low reset
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output wire locked, // PLL is locked signal
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output wire locked, // PLL is locked signal
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//-------- CPU control ----------------------
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//-------- CPU control ----------------------
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output wire clk_cpu, // Generates CPU clock of 3.5 MHz
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output wire clk_cpu, // Generates CPU clock of 3.5 MHz
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output wire vs_nintr, // Generates a vertical retrace interrupt
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output wire vs_nintr, // Generates a vertical retrace interrupt
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//-------- Address and data buses -----------
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//-------- Address and data buses -----------
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input wire [15:0] A, // Input address bus
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input wire [15:0] A, // Input address bus
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input wire [7:0] D, // Input data bus
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input wire [7:0] D, // Input data bus
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output wire [7:0] ula_data, // Output data
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output wire [7:0] ula_data, // Output data
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input wire io_we, // Write enable to data register through IO
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input wire io_we, // Write enable to data register through IO
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output wire [12:0] vram_address,// ULA video block requests a byte from the video RAM
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output wire [12:0] vram_address,// ULA video block requests a byte from the video RAM
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input wire [7:0] vram_data, // ULA video block reads a byte from the video RAM
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input wire [7:0] vram_data, // ULA video block reads a byte from the video RAM
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//-------- PS/2 Keyboard --------------------
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//-------- PS/2 Keyboard --------------------
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input wire PS2_CLK,
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input wire PS2_CLK,
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input wire PS2_DAT,
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input wire PS2_DAT,
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output wire pressed,
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output wire pressed,
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//-------- Audio (Tape player) --------------
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//-------- Audio (Tape player) --------------
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inout wire I2C_SCLK,
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inout wire I2C_SCLK,
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inout wire I2C_SDAT,
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inout wire I2C_SDAT,
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output wire AUD_XCK,
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output wire AUD_XCK,
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output wire AUD_ADCLRCK,
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output wire AUD_ADCLRCK,
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output wire AUD_DACLRCK,
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output wire AUD_DACLRCK,
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output wire AUD_BCLK,
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output wire AUD_BCLK,
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output wire AUD_DACDAT,
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output wire AUD_DACDAT,
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input wire AUD_ADCDAT,
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input wire AUD_ADCDAT,
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output reg beeper,
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output reg beeper,
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//-------- VGA connector --------------------
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//-------- VGA connector --------------------
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output wire [3:0] VGA_R,
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output wire [3:0] VGA_R,
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output wire [3:0] VGA_G,
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output wire [3:0] VGA_G,
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output wire [3:0] VGA_B,
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output wire [3:0] VGA_B,
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output reg VGA_HS,
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output reg VGA_HS,
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output reg VGA_VS
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output reg VGA_VS
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);
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);
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`default_nettype none
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`default_nettype none
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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// Instantiate PLL and clocks block
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// Instantiate PLL and clocks block
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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wire clk_pix; // VGA pixel clock (25.175 MHz)
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wire clk_pix; // VGA pixel clock (25.175 MHz)
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wire clk_ula; // ULA master clock (14 MHz)
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wire clk_ula; // ULA master clock (14 MHz)
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assign clk_vram = clk_pix;
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assign clk_vram = clk_pix;
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pll pll_( .locked(locked), .inclk0(CLOCK_27), .c0(clk_pix), .c1(clk_ula) );
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pll pll_( .locked(locked), .inclk0(CLOCK_27), .c0(clk_pix), .c1(clk_ula) );
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clocks clocks_( .* );
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clocks clocks_( .* );
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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// The border color index
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// The border color index
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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reg [2:0] border; // Border color index value
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reg [2:0] border; // Border color index value
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always @(posedge clk_cpu)
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always @(posedge clk_cpu)
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begin
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begin
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if (A[0]==0 && io_we==1) begin
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if (A[0]==0 && io_we==1) begin
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border <= D[2:0];
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border <= D[2:0];
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// EAR output (produces a louder sound)
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// EAR output (produces a louder sound)
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pcm_outl[14] <= D[4]; // Why [14] and not [15]? Less loud.
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pcm_outl[14] <= D[4]; // Why [14] and not [15]? Less loud.
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pcm_outr[14] <= D[4];
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pcm_outr[14] <= D[4];
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// MIC (echoes the input)
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// MIC (echoes the input)
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pcm_outl[13] <= D[3];
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pcm_outl[13] <= D[3];
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pcm_outr[13] <= D[3];
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pcm_outr[13] <= D[3];
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// Let us hear the tape loading!
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// Let us hear the tape loading!
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pcm_outl[12] <= pcm_inl[14] | pcm_inr[14];
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pcm_outl[12] <= pcm_inl[14] | pcm_inr[14];
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pcm_outr[12] <= pcm_inl[14] | pcm_inr[14];
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pcm_outr[12] <= pcm_inl[14] | pcm_inr[14];
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// Let us see the tape loading!
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// Let us see the tape loading!
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beep <= (pcm_inl[14] | pcm_inr[14]) ^ D[4] ^ D[3];
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beep <= (pcm_inl[14] | pcm_inr[14]) ^ D[4] ^ D[3];
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end
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end
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end
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end
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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// Instantiate audio interface
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// Instantiate audio interface
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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wire audio_done;
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wire audio_done;
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wire audio_error;
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wire audio_error;
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i2c_loader i2c_loader_( .CLK(CLOCK_24), .nRESET(reset), .I2C_SCL(I2C_SCLK), .I2C_SDA(I2C_SDAT), .IS_DONE(audio_done), .IS_ERROR(audio_error) );
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i2c_loader i2c_loader_( .CLK(CLOCK_24), .nRESET(nreset), .I2C_SCL(I2C_SCLK), .I2C_SDA(I2C_SDAT), .IS_DONE(audio_done), .IS_ERROR(audio_error) );
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assign AUD_DACLRCK = AUD_ADCLRCK;
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assign AUD_DACLRCK = AUD_ADCLRCK;
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wire [15:0] pcm_inl;
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wire [15:0] pcm_inl;
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wire [15:0] pcm_inr;
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wire [15:0] pcm_inr;
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reg [15:0] pcm_outl;
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reg [15:0] pcm_outl;
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reg [15:0] pcm_outr;
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reg [15:0] pcm_outr;
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i2s_intf i2s_intf_( .CLK(CLOCK_24), .nRESET(reset),
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i2s_intf i2s_intf_( .CLK(CLOCK_24), .nRESET(nreset),
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.PCM_INL(pcm_inl[15:0]), .PCM_INR(pcm_inr[15:0]), .PCM_OUTL(pcm_outl[15:0]), .PCM_OUTR(pcm_outr[15:0]),
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.PCM_INL(pcm_inl[15:0]), .PCM_INR(pcm_inr[15:0]), .PCM_OUTL(pcm_outl[15:0]), .PCM_OUTR(pcm_outr[15:0]),
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.I2S_MCLK(AUD_XCK), .I2S_LRCLK(AUD_ADCLRCK), .I2S_BCLK(AUD_BCLK), .I2S_DOUT(AUD_DACDAT), .I2S_DIN(AUD_ADCDAT) );
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.I2S_MCLK(AUD_XCK), .I2S_LRCLK(AUD_ADCLRCK), .I2S_BCLK(AUD_BCLK), .I2S_DOUT(AUD_DACDAT), .I2S_DIN(AUD_ADCDAT) );
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// Show the beeper visually by dividing the frequency with some factor to generate blinks
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// Show the beeper visually by dividing the frequency with some factor to generate LED blinks
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reg beep; // Beeper latch
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reg beep; // Beeper latch
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reg [6:0] beepcnt; // Beeper counter
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reg [6:0] beepcnt; // Beeper counter
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always @(posedge beep)
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always @(posedge beep)
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begin
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begin
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beepcnt <= beepcnt - '1;
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beepcnt <= beepcnt - '1;
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if (beepcnt==0) beeper <= ~beeper;
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if (beepcnt==0) beeper <= ~beeper;
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end
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end
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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// Instantiate ULA's video subsystem
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// Instantiate ULA's video subsystem
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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video video_( .* );
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video video_( .* );
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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// Instantiate keyboard support
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// Instantiate keyboard support
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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wire [7:0] scan_code;
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wire [7:0] scan_code;
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wire scan_code_ready;
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wire scan_code_ready;
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wire scan_code_error;
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wire scan_code_error;
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ps2_keyboard ps2_keyboard_( .*, .clk(clk_cpu) );
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ps2_keyboard ps2_keyboard_( .*, .clk(clk_cpu) );
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wire [4:0] key_row;
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wire [4:0] key_row;
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zx_keyboard zx_keyboard_( .*, .clk(clk_cpu) );
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zx_keyboard zx_keyboard_( .*, .clk(clk_cpu) );
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always @(*) // always_comb
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always_comb
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begin
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begin
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ula_data = 8'hFF;
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ula_data = 8'hFF;
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// Regular IO at every odd address: line-in and keyboard
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// Regular IO at every odd address: line-in and keyboard
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if (A[0]==0) begin
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if (A[0]==0) begin
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ula_data = { 1'b0, pcm_inl[14] | pcm_inr[14], 1'b0, key_row[4:0] };
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ula_data = { 1'b0, pcm_inl[14] | pcm_inr[14], 1'b0, key_row[4:0] };
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end
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end
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end
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end
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endmodule
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endmodule
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