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# ----------------------------------------------------
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# ----------------------------------------------------
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# Build Configuration
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# Build Configuration
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# ----------------------------------------------------
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# ----------------------------------------------------
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# AMBER_CLK_DIVIDER
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# Sets the system clock frequency
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# For Spartan-6 divide 800MHz by this number to get the frequency
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# e.g. AMBER_CLK_DIVIDER=24
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# 800 MHz / 24 = 33.33 MHz
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# For Virtex-6 divide 1200MHz by this number to get the frequency
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# Select either the A23 or A25 core
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# Select either the A23 or A25 core
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ifdef A25
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ifdef A25
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AMBER_CORE = AMBER_A25_CORE
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AMBER_CORE = AMBER_A25_CORE
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AMBER_CORE_NAME = a25
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else
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else
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AMBER_CORE = AMBER_A23_CORE
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AMBER_CORE = AMBER_A23_CORE
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AMBER_CORE_NAME = a23
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endif
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endif
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# AMBER_CLK_DIVIDER
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# Sets the system clock frequency
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# Divide 800MHz by this number to get the frequency
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# e.g. AMBER_CLK_DIVIDER=24
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# 800 MHz / 24 = 33.33 MHz
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# The spartan6 device used on SP605 Development board
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# The spartan6 device used on SP605 Development board
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XILINX_FPGA = xc6slx45tfgg484-3
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XILINX_FPGA = xc6slx45tfgg484-3
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XST_DEFINES = XILINX_FPGA XILINX_SPARTAN6_FPGA $(AMBER_CORE) AMBER_CLK_DIVIDER=21 $(BOOT_LOADER_DEF)
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XST_DEFINES = XILINX_FPGA XILINX_SPARTAN6_FPGA $(AMBER_CORE) AMBER_CLK_DIVIDER=18 $(BOOT_LOADER_DEF)
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# Xilinx placement and timing constraints
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# Xilinx placement and timing constraints
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XST_CONST_FILE = xs6_constraints.ucf
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XST_CONST_FILE = xs6_constraints.ucf
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# List of verilog source files for Xilinx Spartan-6 device
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# List of verilog source files for Xilinx Spartan-6 device
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XST_PROJ_FILE = xs6_source_files.prj
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XST_PROJ_FILE = xs6_source_files.prj
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# ----------------------------------------------------
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# ----------------------------------------------------
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$(WORK_FOLDER)/$(RTL_TOP).bit : $(WORK_FOLDER)/$(RTL_TOP).ncd
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$(WORK_FOLDER)/$(RTL_TOP).bit : $(WORK_FOLDER)/$(RTL_TOP).ncd
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\
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\
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cd $(WORK_FOLDER); \
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cd $(WORK_FOLDER); \
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bitgen -intstyle xflow -f $(BIN_FOLDER)/bitfile_config.ut $(RTL_TOP).ncd
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bitgen -intstyle xflow -f $(BIN_FOLDER)/bitfile_config.ut $(RTL_TOP).ncd
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cp $(WORK_FOLDER)/$(RTL_TOP).bit $(BITFILE_FOLDER)/$(RTL_TOP).$(RUN_ID).bit
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cp $(WORK_FOLDER)/$(RTL_TOP).bit $(BITFILE_FOLDER)/$(RTL_TOP).$(AMBER_CORE_NAME).$(RUN_ID).bit
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mv $(WORK_FOLDER)/$(RTL_TOP).bgn $(LOG_FOLDER)/$(RTL_TOP).bit.$(RUN_ID).bgn
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mv $(WORK_FOLDER)/$(RTL_TOP).bgn $(LOG_FOLDER)/$(RTL_TOP).$(AMBER_CORE_NAME).$(RUN_ID).bgn
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# ----------------------------------------------------
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# ----------------------------------------------------
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# par
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# par
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# ----------------------------------------------------
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# ----------------------------------------------------
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