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// Tests sub and subs //
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// Tests sub and subs //
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// //
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// //
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// Author(s): //
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// Author(s): //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// //
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// //
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/*****************************************************************
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// //
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// Amber 2 Core Instruction Test //
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// //
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// This file is part of the Amber project //
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// http://www.opencores.org/project,amber //
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// //
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// Description //
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// Tests sub and subs instructions //
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// //
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// Author(s): //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// //
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//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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// //
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// //
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// Copyright (C) 2010 Authors and OPENCORES.ORG //
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// Copyright (C) 2010 Authors and OPENCORES.ORG //
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// //
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// //
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// This source file may be used and distributed without //
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// This source file may be used and distributed without //
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#include "amber_registers.h"
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#include "amber_registers.h"
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.section .text
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.section .text
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.globl main
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.globl main
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main:
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main:
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@ enable the cache
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ldr r0, =Data1
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mov r0, #0x4
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ldr r6, Data2
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mcr p15, 0, r0, c1, c0, 0
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ldr lr, =1f
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mov pc, lr
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@ Load some bytes into the testbench uart
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@ so it can transmit them to the Amber UART
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ldr r4, AdrTEST_UART_TXD
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ldr r5, =Message
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ldr r7, =EndMessage
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ldr r8, AdrTEST_UART_STATUS
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@ transmit a byte from test uart
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1: ldrb r6, [r5], #1
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str r6, [r4]
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@ full message transmitted?
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cmp r5, r7
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bne 1b
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@ test_uart transmit enable
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ldr r0, AdrTEST_UART_CONTROL
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mov r1, #1
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str r1, [r0]
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/* Enable the UART FIFO */
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ldr r4, AdrUARTLCR
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mov r5, #0x10
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str r5, [r4]
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mov r8, #10
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mov lr, #0x800
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mov sp, #0
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mov r6, #0
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3: mov r0, #1
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bl _inbyte
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add r5, sp, #24
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subs r7, r0, #0
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sub r5, r5, #6
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add r3, r6, #4
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bge 2f
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mov r10, #10
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b testfail
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2: subs r8, r8, #1
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@ Test subs
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beq testpass
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1: ldr r3, [r0]
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b 3b
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subs r2, r3, #1
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cmpcs r2, r6
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movcs r3, #0
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@ r0 is the timeout in mS
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cmp r3, #0
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.globl _inbyte
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_inbyte:
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movne r10, #10
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ldr r1, AdrUARTDR
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bne testfail
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ldr r3, AdrUARTFR
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@ Multiple delay value by 2560
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@ Test sub
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@ as the delay loop takes about 12 clock cycles running cached
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/* 1 - 0x7fffffff */
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@ so that factor gives 1:1mS @33MHz
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ldr r1, MaxPos
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mov r2, r0, lsl #11
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mov r2, #1
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add r2, r2, r0, lsl #9
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sub r3, r2, r1
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ldr r4, MaxNeg
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@ Check the rx empty flag
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add r4, r4, #2
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2: ldr r0, [r3]
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cmp r4, r3
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ands r0, r0, #0x10
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movne r10, #20
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ldreqb r0, [r1]
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bne testfail
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moveq pc, lr
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@ decrement timeout
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subs r2, r2, #1
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bne 2b
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mov r0, #-1
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b testpass
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mov pc, lr
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testfail:
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testfail:
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ldr r11, AdrTestStatus
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ldr r11, AdrTestStatus
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str r10, [r11]
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str r10, [r11]
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Line 99... |
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/* Write 17 to this address to generate a Test Passed message */
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/* Write 17 to this address to generate a Test Passed message */
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AdrTestStatus: .word ADR_AMBER_TEST_STATUS
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AdrTestStatus: .word ADR_AMBER_TEST_STATUS
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MaxPos: .word 0x7fffffff
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MaxPos: .word 0x7fffffff
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AdrUARTDR: .word ADR_AMBER_UART0_DR
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MaxNeg: .word 0x80000000
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AdrUARTFR: .word ADR_AMBER_UART0_FR
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Data1: .word 0x03000000
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AdrUARTLCR: .word ADR_AMBER_UART0_LCRH
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Data2: .word 0x020febed
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AdrTEST_UART_CONTROL: .word ADR_AMBER_TEST_UART_CONTROL
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AdrTEST_UART_STATUS: .word ADR_AMBER_TEST_UART_STATUS
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AdrTEST_UART_TXD: .word ADR_AMBER_TEST_UART_TXD
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Message: .ascii "abcdefghijkl"
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EndMessage: .word 0
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/* ========================================================================= */
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/* ========================================================================= */
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/* ========================================================================= */
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/* ========================================================================= */
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