OpenCores
URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] [amber/] [trunk/] [hw/] [tests/] [sub.S] - Diff between revs 2 and 11

Only display areas with differences | Details | Blame | View Log

Rev 2 Rev 11
/*****************************************************************
/*****************************************************************
//                                                              //
//                                                              //
//  Amber 2 Core Instruction Test                               //
//  Amber 2 Core Instruction Test                               //
//                                                              //
//                                                              //
//  This file is part of the Amber project                      //
//  This file is part of the Amber project                      //
//  http://www.opencores.org/project,amber                      //
//  http://www.opencores.org/project,amber                      //
//                                                              //
//                                                              //
//  Description                                                 //
//  Description                                                 //
//  Tests sub and subs                                          //
//  Tests sub and subs                                          //
//                                                              //
//                                                              //
//  Author(s):                                                  //
//  Author(s):                                                  //
//      - Conor Santifort, csantifort.amber@gmail.com           //
//      - Conor Santifort, csantifort.amber@gmail.com           //
//                                                              //
//                                                              //
 
/*****************************************************************
 
//                                                              //
 
//  Amber 2 Core Instruction Test                               //
 
//                                                              //
 
//  This file is part of the Amber project                      //
 
//  http://www.opencores.org/project,amber                      //
 
//                                                              //
 
//  Description                                                 //
 
//  Tests sub and subs instructions                             //
 
//                                                              //
 
//  Author(s):                                                  //
 
//      - Conor Santifort, csantifort.amber@gmail.com           //
 
//                                                              //
//////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////
//                                                              //
//                                                              //
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
//                                                              //
//                                                              //
// This source file may be used and distributed without         //
// This source file may be used and distributed without         //
// restriction provided that this copyright statement is not    //
// restriction provided that this copyright statement is not    //
// removed from the file and that any derivative work contains  //
// removed from the file and that any derivative work contains  //
// the original copyright notice and the associated disclaimer. //
// the original copyright notice and the associated disclaimer. //
//                                                              //
//                                                              //
// This source file is free software; you can redistribute it   //
// This source file is free software; you can redistribute it   //
// and/or modify it under the terms of the GNU Lesser General   //
// and/or modify it under the terms of the GNU Lesser General   //
// Public License as published by the Free Software Foundation; //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any   //
// either version 2.1 of the License, or (at your option) any   //
// later version.                                               //
// later version.                                               //
//                                                              //
//                                                              //
// This source is distributed in the hope that it will be       //
// This source is distributed in the hope that it will be       //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// PURPOSE.  See the GNU Lesser General Public License for more //
// PURPOSE.  See the GNU Lesser General Public License for more //
// details.                                                     //
// details.                                                     //
//                                                              //
//                                                              //
// You should have received a copy of the GNU Lesser General    //
// You should have received a copy of the GNU Lesser General    //
// Public License along with this source; if not, download it   //
// Public License along with this source; if not, download it   //
// from http://www.opencores.org/lgpl.shtml                     //
// from http://www.opencores.org/lgpl.shtml                     //
//                                                              //
//                                                              //
*****************************************************************/
*****************************************************************/
#include "amber_registers.h"
#include "amber_registers.h"
        .section .text
        .section .text
        .globl  main
        .globl  main
main:
main:
        @ enable the cache
        ldr     r0, =Data1
        mov     r0,  #0x4
        ldr     r6, Data2
        mcr     p15, 0, r0, c1, c0, 0
        ldr     lr, =1f
 
        mov     pc, lr
        @ Load some bytes into the testbench uart
 
        @ so it can transmit them to the Amber UART
 
        ldr     r4, AdrTEST_UART_TXD
 
        ldr     r5, =Message
 
        ldr     r7, =EndMessage
 
        ldr     r8, AdrTEST_UART_STATUS
 
 
 
        @ transmit a byte from test uart
 
1:      ldrb    r6, [r5], #1
 
        str     r6, [r4]
 
 
 
        @ full message transmitted?
 
        cmp     r5, r7
 
        bne     1b
 
 
 
        @ test_uart transmit enable
 
        ldr     r0, AdrTEST_UART_CONTROL
 
        mov     r1, #1
 
        str     r1, [r0]
 
 
 
        /* Enable the UART FIFO */
 
        ldr     r4, AdrUARTLCR
 
        mov     r5, #0x10
 
        str     r5, [r4]
 
 
 
        mov     r8, #10
 
        mov     lr, #0x800
 
        mov     sp, #0
 
        mov     r6, #0
 
 
 
3:      mov     r0, #1
 
        bl      _inbyte
 
        add     r5, sp, #24
 
        subs    r7, r0, #0
 
        sub     r5, r5, #6
 
        add     r3, r6, #4
 
        bge     2f
 
 
 
        mov     r10, #10
 
        b       testfail
 
 
 
2:      subs    r8, r8, #1
        @ Test subs
        beq     testpass
1:      ldr     r3, [r0]
        b       3b
        subs    r2,  r3,  #1
 
        cmpcs   r2,  r6
 
        movcs   r3,  #0
        @ r0 is the timeout in mS
        cmp     r3,  #0
        .globl _inbyte
 
_inbyte:
        movne   r10, #10
        ldr     r1, AdrUARTDR
        bne     testfail
        ldr     r3, AdrUARTFR
 
 
 
        @ Multiple delay value by 2560
        @ Test sub
        @ as the delay loop takes about 12 clock cycles running cached
/* 1 - 0x7fffffff */
        @ so that factor gives 1:1mS @33MHz
        ldr     r1, MaxPos
        mov     r2, r0, lsl #11
        mov     r2, #1
        add     r2, r2, r0, lsl #9
        sub     r3, r2, r1
 
        ldr     r4, MaxNeg
        @ Check the rx empty flag
        add     r4, r4, #2
2:      ldr     r0, [r3]
        cmp     r4, r3
        ands    r0, r0, #0x10
        movne   r10, #20
        ldreqb  r0, [r1]
        bne     testfail
        moveq   pc, lr
 
 
 
        @ decrement timeout
 
        subs    r2, r2, #1
 
        bne     2b
 
 
 
        mov     r0, #-1
        b       testpass
        mov     pc, lr
 
 
 
testfail:
testfail:
        ldr     r11, AdrTestStatus
        ldr     r11, AdrTestStatus
        str     r10, [r11]
        str     r10, [r11]
        b       testfail
        b       testfail
testpass:
testpass:
        ldr     r11, AdrTestStatus
        ldr     r11, AdrTestStatus
        mov     r10, #17
        mov     r10, #17
        str     r10, [r11]
        str     r10, [r11]
        b       testpass
        b       testpass
/* Write 17 to this address to generate a Test Passed message */
/* Write 17 to this address to generate a Test Passed message */
AdrTestStatus:  .word  ADR_AMBER_TEST_STATUS
AdrTestStatus:  .word  ADR_AMBER_TEST_STATUS
MaxPos:         .word  0x7fffffff
MaxPos:         .word  0x7fffffff
AdrUARTDR:      .word  ADR_AMBER_UART0_DR
MaxNeg:         .word  0x80000000
AdrUARTFR:      .word  ADR_AMBER_UART0_FR
Data1:          .word  0x03000000
AdrUARTLCR:     .word  ADR_AMBER_UART0_LCRH
Data2:          .word  0x020febed
 
 
AdrTEST_UART_CONTROL:   .word  ADR_AMBER_TEST_UART_CONTROL
 
AdrTEST_UART_STATUS:    .word  ADR_AMBER_TEST_UART_STATUS
 
AdrTEST_UART_TXD:       .word  ADR_AMBER_TEST_UART_TXD
 
 
 
Message:                .ascii "abcdefghijkl"
 
EndMessage:             .word  0
 
 
 
/* ========================================================================= */
/* ========================================================================= */
/* ========================================================================= */
/* ========================================================================= */
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.