//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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// //
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// //
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// Barrel Shifter for Amber 2 Core //
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// Barrel Shifter for Amber 2 Core //
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// //
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// //
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// The design is optimized for Altera family of FPGAs, //
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// The design is optimized for Altera family of FPGAs, //
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// and it can be used directly or adapted other N-to-1 LUT //
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// and it can be used directly or adapted other N-to-1 LUT //
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// FPGA platforms. //
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// FPGA platforms. //
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// //
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// //
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// This file is part of the Amber project //
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// This file is part of the Amber project //
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// http://www.opencores.org/project,amber //
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// http://www.opencores.org/project,amber //
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// //
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// //
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// Description //
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// Description //
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// Provides 32-bit shifts LSL, LSR, ASR and ROR //
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// Provides 32-bit shifts LSL, LSR, ASR and ROR //
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// //
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// //
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// Author(s): //
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// Author(s): //
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// - Dmitry Tarnyagin, dmitry.tarnyagin@lockless.no //
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// - Dmitry Tarnyagin, dmitry.tarnyagin@lockless.no //
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// //
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// //
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//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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// //
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// //
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// Copyright (C) 2010-2013 Authors and OPENCORES.ORG //
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// Copyright (C) 2010-2013 Authors and OPENCORES.ORG //
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// //
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// //
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// This source file may be used and distributed without //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// the original copyright notice and the associated disclaimer. //
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// //
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// //
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// This source file is free software; you can redistribute it //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// later version. //
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// //
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// //
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// This source is distributed in the hope that it will be //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// details. //
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// //
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// //
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// You should have received a copy of the GNU Lesser General //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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// //
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//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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module a23_barrel_shift_fpga (
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module a23_barrel_shift_fpga (
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input [31:0] i_in,
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input [31:0] i_in,
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input i_carry_in,
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input i_carry_in,
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input [7:0] i_shift_amount, // uses 8 LSBs of Rs, or a 5 bit immediate constant
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input [7:0] i_shift_amount, // uses 8 LSBs of Rs, or a 5 bit immediate constant
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input i_shift_imm_zero, // high when immediate shift value of zero selected
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input i_shift_imm_zero, // high when immediate shift value of zero selected
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input [1:0] i_function,
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input [1:0] i_function,
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output [31:0] o_out,
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output [31:0] o_out,
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output o_carry_out
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output o_carry_out
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);
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);
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`include "a23_localparams.v"
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`include "a23_localparams.vh"
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wire [31:0] rot_prod; // Input rotated by the shift amount
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wire [31:0] rot_prod; // Input rotated by the shift amount
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wire [1:0] lsl_out; // LSL: {carry, bit_31}
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wire [1:0] lsl_out; // LSL: {carry, bit_31}
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wire [1:0] lsr_out; // LSR: {carry, bit_31}
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wire [1:0] lsr_out; // LSR: {carry, bit_31}
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wire [1:0] asr_out; // ASR: {carry, bit_31}
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wire [1:0] asr_out; // ASR: {carry, bit_31}
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wire [1:0] ror_out; // ROR: {carry, bit_31}
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wire [1:0] ror_out; // ROR: {carry, bit_31}
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reg [32:0] lsl_mask; // Left-hand mask
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reg [32:0] lsl_mask; // Left-hand mask
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reg [32:0] lsr_mask; // Right-hand mask
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reg [32:0] lsr_mask; // Right-hand mask
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reg [15:0] low_mask; // Mask calculation helper
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reg [15:0] low_mask; // Mask calculation helper
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reg [4:0] shift_amount; // Shift amount for the low-level shifter
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reg [4:0] shift_amount; // Shift amount for the low-level shifter
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reg [2:0] lsl_selector; // Left shift {shift_32, shift_over, shift_amount[4]}
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reg [2:0] lsl_selector; // Left shift {shift_32, shift_over, shift_amount[4]}
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reg [2:0] lsr_selector; // Right shift {shift_32, shift_over, shift_amount[4]}
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reg [2:0] lsr_selector; // Right shift {shift_32, shift_over, shift_amount[4]}
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reg [3:0] low_selector; // {shift_amount[3:0]}
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reg [3:0] low_selector; // {shift_amount[3:0]}
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reg shift_nzero; // Amount is not zero
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reg shift_nzero; // Amount is not zero
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reg shift_over; // Amount is 32 or higher
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reg shift_over; // Amount is 32 or higher
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reg shift_32; // Amount is exactly 32
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reg shift_32; // Amount is exactly 32
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reg asr_sign; // Sign for ASR shift
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reg asr_sign; // Sign for ASR shift
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reg direction; // Shift direction
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reg direction; // Shift direction
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wire [31:0] p_r; // 1 bit rotated rot_prod
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wire [31:0] p_r; // 1 bit rotated rot_prod
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wire [31:0] p_l; // Alias for the rot_prod
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wire [31:0] p_l; // Alias for the rot_prod
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// Implementation details:
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// Implementation details:
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// Design is based on masking of rotated input by a left- and right- hand masks.
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// Design is based on masking of rotated input by a left- and right- hand masks.
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// Rotated product calculation requires 5 levels of combinational logic, and masks
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// Rotated product calculation requires 5 levels of combinational logic, and masks
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// must be ready before the product is ready. In fact masks require just 3 to 4 levels
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// must be ready before the product is ready. In fact masks require just 3 to 4 levels
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// of logic cells using 4-to-1/2x3-to-1 Altera.
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// of logic cells using 4-to-1/2x3-to-1 Altera.
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always @*
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always @*
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begin
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begin
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shift_32 = i_shift_amount == 32;
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shift_32 = i_shift_amount == 32;
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shift_over = |i_shift_amount[7:5];
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shift_over = |i_shift_amount[7:5];
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shift_nzero = |i_shift_amount[7:0];
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shift_nzero = |i_shift_amount[7:0];
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shift_amount = i_shift_amount[4:0];
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shift_amount = i_shift_amount[4:0];
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if (i_shift_imm_zero) begin
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if (i_shift_imm_zero) begin
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if (i_function == LSR || i_function == ASR) begin
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if (i_function == LSR || i_function == ASR) begin
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// The form of the shift field which might be
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// The form of the shift field which might be
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// expected to correspond to LSR #0 is used
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// expected to correspond to LSR #0 is used
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// to encode LSR #32, which has a zero result
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// to encode LSR #32, which has a zero result
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// with bit 31 of Rm as the carry output.
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// with bit 31 of Rm as the carry output.
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shift_nzero = 1'b1;
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shift_nzero = 1'b1;
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shift_over = 1'b1;
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shift_over = 1'b1;
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// Redundant and can be optimized out
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// Redundant and can be optimized out
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// shift_32 = 1'b1;
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// shift_32 = 1'b1;
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end else if (i_function == ROR) begin
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end else if (i_function == ROR) begin
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// RXR, (ROR w/ imm 0)
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// RXR, (ROR w/ imm 0)
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shift_amount[0] = 1'b1;
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shift_amount[0] = 1'b1;
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shift_nzero = 1'b1;
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shift_nzero = 1'b1;
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end
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end
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end
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end
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// LSB sub-selector calculation. Usually it is taken
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// LSB sub-selector calculation. Usually it is taken
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// directly from the shift_amount, but ROR requires
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// directly from the shift_amount, but ROR requires
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// no masking at all.
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// no masking at all.
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case (i_function)
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case (i_function)
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LSL: low_selector = shift_amount[3:0];
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LSL: low_selector = shift_amount[3:0];
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LSR: low_selector = shift_amount[3:0];
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LSR: low_selector = shift_amount[3:0];
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ASR: low_selector = shift_amount[3:0];
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ASR: low_selector = shift_amount[3:0];
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ROR: low_selector = 4'b0000;
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ROR: low_selector = 4'b0000;
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endcase
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endcase
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// Left-hand MSB sub-selector calculation. Opaque for every function but LSL.
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// Left-hand MSB sub-selector calculation. Opaque for every function but LSL.
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case (i_function)
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case (i_function)
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LSL: lsl_selector = {shift_32, shift_over, shift_amount[4]};
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LSL: lsl_selector = {shift_32, shift_over, shift_amount[4]};
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LSR: lsl_selector = 3'b0_1_0; // Opaque mask selector
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LSR: lsl_selector = 3'b0_1_0; // Opaque mask selector
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ASR: lsl_selector = 3'b0_1_0; // Opaque mask selector
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ASR: lsl_selector = 3'b0_1_0; // Opaque mask selector
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ROR: lsl_selector = 3'b0_1_0; // Opaque mask selector
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ROR: lsl_selector = 3'b0_1_0; // Opaque mask selector
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endcase
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endcase
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// Right-hand MSB sub-selector calculation. Opaque for LSL, transparent for ROR.
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// Right-hand MSB sub-selector calculation. Opaque for LSL, transparent for ROR.
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case (i_function)
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case (i_function)
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LSL: lsr_selector = 3'b0_1_0; // Opaque mask selector
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LSL: lsr_selector = 3'b0_1_0; // Opaque mask selector
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LSR: lsr_selector = {shift_32, shift_over, shift_amount[4]};
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LSR: lsr_selector = {shift_32, shift_over, shift_amount[4]};
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ASR: lsr_selector = {shift_32, shift_over, shift_amount[4]};
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ASR: lsr_selector = {shift_32, shift_over, shift_amount[4]};
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ROR: lsr_selector = 3'b0_0_0; // Transparent mask selector
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ROR: lsr_selector = 3'b0_0_0; // Transparent mask selector
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endcase
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endcase
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// Direction
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// Direction
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case (i_function)
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case (i_function)
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LSL: direction = 1'b0; // Left shift
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LSL: direction = 1'b0; // Left shift
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LSR: direction = 1'b1; // Right shift
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LSR: direction = 1'b1; // Right shift
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ASR: direction = 1'b1; // Right shift
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ASR: direction = 1'b1; // Right shift
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ROR: direction = 1'b1; // Right shift
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ROR: direction = 1'b1; // Right shift
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endcase
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endcase
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// Sign for ASR shift
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// Sign for ASR shift
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asr_sign = 1'b0;
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asr_sign = 1'b0;
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if (i_function == ASR && i_in[31])
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if (i_function == ASR && i_in[31])
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asr_sign = 1'b1;
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asr_sign = 1'b1;
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end
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end
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// Generic rotate. Theoretical cost: 32x5 4-to-1 LUTs.
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// Generic rotate. Theoretical cost: 32x5 4-to-1 LUTs.
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// Practically a bit higher due to high fanout of "direction".
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// Practically a bit higher due to high fanout of "direction".
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generate
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generate
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genvar i, j;
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genvar i, j;
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for (i = 0; i < 5; i = i + 1)
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for (i = 0; i < 5; i = i + 1)
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begin : netgen
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begin : netgen
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wire [31:0] in;
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wire [31:0] in;
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reg [31:0] out;
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reg [31:0] out;
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for (j = 0; j < 32; j = j + 1)
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for (j = 0; j < 32; j = j + 1)
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begin : net
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begin : net
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always @*
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always @*
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out[j] = in[j] & (~shift_amount[i] ^ direction) |
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out[j] = in[j] & (~shift_amount[i] ^ direction) |
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in[wrap(j, i)] & (shift_amount[i] ^ direction);
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in[wrap(j, i)] & (shift_amount[i] ^ direction);
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end
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end
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end
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end
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// Order is reverted with respect to volatile shift_amount[0]
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// Order is reverted with respect to volatile shift_amount[0]
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assign netgen[4].in = i_in;
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assign netgen[4].in = i_in;
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for (i = 1; i < 5; i = i + 1)
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for (i = 1; i < 5; i = i + 1)
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begin : router
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begin : router
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assign netgen[i-1].in = netgen[i].out;
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assign netgen[i-1].in = netgen[i].out;
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end
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end
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endgenerate
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endgenerate
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// Aliasing
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// Aliasing
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assign rot_prod = netgen[0].out;
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assign rot_prod = netgen[0].out;
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// Submask calculated from LSB sub-selector.
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// Submask calculated from LSB sub-selector.
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// Cost: 16 4-to-1 LUTs.
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// Cost: 16 4-to-1 LUTs.
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always @*
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always @*
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case (low_selector) // synthesis full_case parallel_case
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case (low_selector) // synthesis full_case parallel_case
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4'b0000: low_mask = 16'hffff;
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4'b0000: low_mask = 16'hffff;
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4'b0001: low_mask = 16'hfffe;
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4'b0001: low_mask = 16'hfffe;
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4'b0010: low_mask = 16'hfffc;
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4'b0010: low_mask = 16'hfffc;
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4'b0011: low_mask = 16'hfff8;
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4'b0011: low_mask = 16'hfff8;
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4'b0100: low_mask = 16'hfff0;
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4'b0100: low_mask = 16'hfff0;
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4'b0101: low_mask = 16'hffe0;
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4'b0101: low_mask = 16'hffe0;
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4'b0110: low_mask = 16'hffc0;
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4'b0110: low_mask = 16'hffc0;
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4'b0111: low_mask = 16'hff80;
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4'b0111: low_mask = 16'hff80;
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4'b1000: low_mask = 16'hff00;
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4'b1000: low_mask = 16'hff00;
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4'b1001: low_mask = 16'hfe00;
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4'b1001: low_mask = 16'hfe00;
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4'b1010: low_mask = 16'hfc00;
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4'b1010: low_mask = 16'hfc00;
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4'b1011: low_mask = 16'hf800;
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4'b1011: low_mask = 16'hf800;
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4'b1100: low_mask = 16'hf000;
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4'b1100: low_mask = 16'hf000;
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4'b1101: low_mask = 16'he000;
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4'b1101: low_mask = 16'he000;
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4'b1110: low_mask = 16'hc000;
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4'b1110: low_mask = 16'hc000;
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4'b1111: low_mask = 16'h8000;
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4'b1111: low_mask = 16'h8000;
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endcase
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endcase
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// Left-hand mask calculation.
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// Left-hand mask calculation.
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// Cost: 33 4-to-1 LUTs.
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// Cost: 33 4-to-1 LUTs.
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always @*
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always @*
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casez (lsl_selector) // synthesis full_case parallel_case
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casez (lsl_selector) // synthesis full_case parallel_case
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7'b1??: lsl_mask = 33'h_1_0000_0000;
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7'b1??: lsl_mask = 33'h_1_0000_0000;
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7'b01?: lsl_mask = 33'h_0_0000_0000;
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7'b01?: lsl_mask = 33'h_0_0000_0000;
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7'b001: lsl_mask = { 1'h_1, low_mask, 16'h_0000};
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7'b001: lsl_mask = { 1'h_1, low_mask, 16'h_0000};
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7'b000: lsl_mask = {17'h_1_ffff, low_mask};
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7'b000: lsl_mask = {17'h_1_ffff, low_mask};
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endcase
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endcase
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// Right-hand mask calculation.
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// Right-hand mask calculation.
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// Cost: 33 4-to-1 LUTs.
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// Cost: 33 4-to-1 LUTs.
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always @*
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always @*
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casez (lsr_selector) // synthesis full_case parallel_case
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casez (lsr_selector) // synthesis full_case parallel_case
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7'b1??: lsr_mask = 33'h_1_0000_0000;
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7'b1??: lsr_mask = 33'h_1_0000_0000;
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7'b01?: lsr_mask = 33'h_0_0000_0000;
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7'b01?: lsr_mask = 33'h_0_0000_0000;
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7'b000: lsr_mask = { 1'h_1, bit_swap(low_mask), 16'h_ffff};
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7'b000: lsr_mask = { 1'h_1, bit_swap(low_mask), 16'h_ffff};
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7'b001: lsr_mask = {17'h_1_0000, bit_swap(low_mask)};
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7'b001: lsr_mask = {17'h_1_0000, bit_swap(low_mask)};
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endcase
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endcase
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// Alias: right-rotated
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// Alias: right-rotated
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assign p_r = {rot_prod[30:0], rot_prod[31]};
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assign p_r = {rot_prod[30:0], rot_prod[31]};
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// Alias: left-rotated
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// Alias: left-rotated
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assign p_l = rot_prod[31:0];
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assign p_l = rot_prod[31:0];
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// ROR MSB, handling special cases
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// ROR MSB, handling special cases
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assign ror_out[0] = i_shift_imm_zero ? i_carry_in :
|
assign ror_out[0] = i_shift_imm_zero ? i_carry_in :
|
p_r[31];
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p_r[31];
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|
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// ROR carry, handling special cases
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// ROR carry, handling special cases
|
assign ror_out[1] = i_shift_imm_zero ? i_in[0] :
|
assign ror_out[1] = i_shift_imm_zero ? i_in[0] :
|
shift_nzero ? p_r[31] :
|
shift_nzero ? p_r[31] :
|
i_carry_in;
|
i_carry_in;
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|
|
// LSL MSB
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// LSL MSB
|
assign lsl_out[0] = p_l[31] & lsl_mask[31];
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assign lsl_out[0] = p_l[31] & lsl_mask[31];
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|
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// LSL carry, handling special cases
|
// LSL carry, handling special cases
|
assign lsl_out[1] = shift_nzero ? p_l[0] & lsl_mask[32]:
|
assign lsl_out[1] = shift_nzero ? p_l[0] & lsl_mask[32]:
|
i_carry_in;
|
i_carry_in;
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|
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// LSR MSB
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// LSR MSB
|
assign lsr_out[0] = p_r[31] & lsr_mask[31];
|
assign lsr_out[0] = p_r[31] & lsr_mask[31];
|
|
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// LSR carry, handling special cases
|
// LSR carry, handling special cases
|
assign lsr_out[1] = i_shift_imm_zero ? i_in[31] :
|
assign lsr_out[1] = i_shift_imm_zero ? i_in[31] :
|
shift_nzero ? p_r[31] & lsr_mask[32]:
|
shift_nzero ? p_r[31] & lsr_mask[32]:
|
i_carry_in;
|
i_carry_in;
|
|
|
// ASR MSB
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// ASR MSB
|
assign asr_out[0] = i_in[31] ? i_in[31] :
|
assign asr_out[0] = i_in[31] ? i_in[31] :
|
p_r[31] & lsr_mask[31] ;
|
p_r[31] & lsr_mask[31] ;
|
|
|
// LSR carry, handling special cases
|
// LSR carry, handling special cases
|
assign asr_out[1] = shift_over ? i_in[31] :
|
assign asr_out[1] = shift_over ? i_in[31] :
|
shift_nzero ? p_r[31] :
|
shift_nzero ? p_r[31] :
|
i_carry_in;
|
i_carry_in;
|
|
|
// Carry and MSB are calculated as above
|
// Carry and MSB are calculated as above
|
assign {o_carry_out, o_out[31]} = i_function == LSL ? lsl_out :
|
assign {o_carry_out, o_out[31]} = i_function == LSL ? lsl_out :
|
i_function == LSR ? lsr_out :
|
i_function == LSR ? lsr_out :
|
i_function == ASR ? asr_out :
|
i_function == ASR ? asr_out :
|
ror_out ;
|
ror_out ;
|
|
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// And the rest of result is the masked rotated input.
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// And the rest of result is the masked rotated input.
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assign o_out[30:0] = (p_l[30:0] & lsl_mask[30:0]) |
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assign o_out[30:0] = (p_l[30:0] & lsl_mask[30:0]) |
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(p_r[30:0] & lsr_mask[30:0]) |
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(p_r[30:0] & lsr_mask[30:0]) |
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(~lsr_mask[30:0] & {31{asr_sign}});
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(~lsr_mask[30:0] & {31{asr_sign}});
|
|
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// Rotate: calculate bit pos for level "level" and offset "pos"
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// Rotate: calculate bit pos for level "level" and offset "pos"
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function [4:0] wrap;
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function [4:0] wrap;
|
input integer pos;
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input integer pos;
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input integer level;
|
input integer level;
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integer out;
|
integer out;
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begin
|
begin
|
out = pos - (1 << level);
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out = pos - (1 << level);
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wrap = out[4:0];
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wrap = out[4:0];
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end
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end
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endfunction
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endfunction
|
|
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// Swap bits in the input 16-bit value
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// Swap bits in the input 16-bit value
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function [15:0] bit_swap;
|
function [15:0] bit_swap;
|
input [15:0] value;
|
input [15:0] value;
|
integer i;
|
integer i;
|
begin
|
begin
|
for (i = 0; i < 16; i = i + 1)
|
for (i = 0; i < 16; i = i + 1)
|
bit_swap[i] = value[15 - i];
|
bit_swap[i] = value[15 - i];
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end
|
end
|
endfunction
|
endfunction
|
|
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endmodule
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endmodule
|
|
|
