| Line 94... |
Line 94... |
input i_cache_enable, // from co-processor 15 configuration register
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input i_cache_enable, // from co-processor 15 configuration register
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input i_cache_flush, // from co-processor 15 register
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input i_cache_flush, // from co-processor 15 register
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output [31:0] o_read_data,
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output [31:0] o_read_data,
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input i_fetch_stall,
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input i_fetch_stall,
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input i_exec_stall,
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output o_stall,
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output o_stall,
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// WB Read Request
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// WB Read Request
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output o_wb_req, // Read Request
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output o_wb_cached_req, // Read Request
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input [31:0] i_wb_read_data, // wb bus
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input [127:0] i_wb_cached_rdata, // wb bus
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input i_wb_ready // wb_stb && !wb_ack
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input i_wb_cached_ready // wb_stb && !wb_ack
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);
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);
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`include "a25_localparams.v"
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`include "a25_localparams.v"
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`include "a25_functions.v"
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`include "a25_functions.v"
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| Line 167... |
Line 168... |
wire [CACHE_LINE_WIDTH-1:0] hit_rdata;
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wire [CACHE_LINE_WIDTH-1:0] hit_rdata;
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wire read_stall;
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wire read_stall;
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wire write_stall;
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wire write_stall;
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wire cache_busy_stall;
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wire cache_busy_stall;
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wire access_stall;
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wire core_stall;
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wire write_state;
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wire write_state;
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wire request_pulse;
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wire request_pulse;
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wire request_hold;
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wire request_hold;
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reg request_r = 'd0;
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reg request_r = 'd0;
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| Line 187... |
Line 188... |
wire ex_read_cache_busy;
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wire ex_read_cache_busy;
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reg [31:0] wb_address = 'd0;
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reg [31:0] wb_address = 'd0;
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wire rbuf_hit = 'd0;
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wire rbuf_hit = 'd0;
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wire wb_hit;
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wire wb_hit;
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wire [127:0] read_data128;
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genvar i;
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genvar i;
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// ======================================
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// ======================================
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// Address to use for cache access
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// Address to use for cache access
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// ======================================
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// ======================================
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// If currently stalled then the address for the next
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// If currently stalled then the address for the next
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// cycle will be the same as it is in the current cycle
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// cycle will be the same as it is in the current cycle
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//
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//
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assign access_stall = i_fetch_stall || o_stall;
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assign core_stall = i_fetch_stall || i_exec_stall || o_stall;
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assign address = access_stall ? i_address [CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] :
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assign address = core_stall ? i_address [CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] :
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i_address_nxt[CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] ;
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i_address_nxt[CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] ;
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// ======================================
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// ======================================
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// Outputs
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// Outputs
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// ======================================
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// ======================================
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assign o_read_data = wb_hit ? i_wb_read_data :
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i_address[WORD_SEL_MSB:WORD_SEL_LSB] == 2'd0 ? hit_rdata [31:0] :
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assign read_data128 = wb_hit ? i_wb_cached_rdata : hit_rdata;
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i_address[WORD_SEL_MSB:WORD_SEL_LSB] == 2'd1 ? hit_rdata [63:32] :
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i_address[WORD_SEL_MSB:WORD_SEL_LSB] == 2'd2 ? hit_rdata [95:64] :
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assign o_read_data = i_address[WORD_SEL_MSB:WORD_SEL_LSB] == 2'd0 ? read_data128 [31:0] :
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hit_rdata [127:96] ;
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i_address[WORD_SEL_MSB:WORD_SEL_LSB] == 2'd1 ? read_data128 [63:32] :
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i_address[WORD_SEL_MSB:WORD_SEL_LSB] == 2'd2 ? read_data128 [95:64] :
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read_data128 [127:96] ;
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// Don't allow the cache to stall the wb i/f for an exclusive access
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// Don't allow the cache to stall the wb i/f for an exclusive access
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// The cache needs a couple of cycles to flush a potential copy of the exclusive
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// The cache needs a couple of cycles to flush a potential copy of the exclusive
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// address, but the wb can do the access in parallel. So there is no
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// address, but the wb can do the access in parallel. So there is no
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// stall in the state CS_EX_DELETE, even though the cache is out of action.
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// stall in the state CS_EX_DELETE, even though the cache is out of action.
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// This works fine as long as the wb is stalling the core
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// This works fine as long as the wb is stalling the core
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assign o_stall = request_hold && ( read_stall || write_stall || cache_busy_stall || ex_read_cache_busy );
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assign o_stall = request_hold && ( read_stall || write_stall || cache_busy_stall || ex_read_cache_busy );
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assign o_wb_req = ( (read_miss || write_miss || write_hit) && c_state == CS_IDLE ) || consecutive_write;
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assign o_wb_cached_req = ( (read_miss || write_miss || write_hit) && c_state == CS_IDLE ) || consecutive_write;
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// ======================================
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// ======================================
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// Cache State Machine
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// Cache State Machine
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// ======================================
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// ======================================
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| Line 261... |
Line 264... |
select_way <= data_hit_way | ex_read_hit_way;
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select_way <= data_hit_way | ex_read_hit_way;
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c_state <= CS_EX_DELETE;
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c_state <= CS_EX_DELETE;
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source_sel <= 1'd1 << C_INVA;
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source_sel <= 1'd1 << C_INVA;
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end
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end
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else if ( read_miss )
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else if ( read_miss )
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c_state <= CS_FILL0;
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c_state <= CS_FILL3;
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else if ( write_hit )
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else if ( write_hit )
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begin
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begin
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if ( i_wb_ready )
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if ( i_wb_cached_ready )
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c_state <= CS_WRITE_HIT1;
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c_state <= CS_WRITE_HIT1;
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else
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else
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c_state <= CS_WRITE_HIT_WAIT_WB;
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c_state <= CS_WRITE_HIT_WAIT_WB;
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end
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end
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else if ( write_miss && !i_wb_ready )
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else if ( write_miss && !i_wb_cached_ready )
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c_state <= CS_WRITE_MISS_WAIT_WB;
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c_state <= CS_WRITE_MISS_WAIT_WB;
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end
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end
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CS_FILL0 :
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// wb read request asserted, wait for ack
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if ( i_wb_ready )
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c_state <= CS_FILL1;
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CS_FILL1 :
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// first read of burst of 4
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// wb read request asserted, wait for ack
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if ( i_wb_ready )
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c_state <= CS_FILL2;
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CS_FILL2 :
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// second read of burst of 4
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// wb read request asserted, wait for ack
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if ( i_wb_ready )
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c_state <= CS_FILL3;
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CS_FILL3 :
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CS_FILL3 :
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// third read of burst of 4
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// third read of burst of 4
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// wb read request asserted, wait for ack
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// wb read request asserted, wait for ack
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if ( i_wb_ready )
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if ( i_wb_cached_ready )
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begin
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begin
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c_state <= CS_FILL_COMPLETE;
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c_state <= CS_FILL_COMPLETE;
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source_sel <= 1'd1 << C_FILL;
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source_sel <= 1'd1 << C_FILL;
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// Pick a way to write the cache update into
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// Pick a way to write the cache update into
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| Line 351... |
Line 334... |
c_state <= CS_IDLE;
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c_state <= CS_IDLE;
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CS_WRITE_HIT_WAIT_WB:
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CS_WRITE_HIT_WAIT_WB:
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// wait for an ack on the wb bus to complete the write
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// wait for an ack on the wb bus to complete the write
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if ( i_wb_ready )
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if ( i_wb_cached_ready )
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c_state <= CS_IDLE;
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c_state <= CS_IDLE;
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CS_WRITE_MISS_WAIT_WB:
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CS_WRITE_MISS_WAIT_WB:
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// wait for an ack on the wb bus to complete the write
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// wait for an ack on the wb bus to complete the write
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if ( i_wb_ready )
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if ( i_wb_cached_ready )
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c_state <= CS_IDLE;
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c_state <= CS_IDLE;
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endcase
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endcase
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// ======================================
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// ======================================
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// Capture WB Block Read - burst of 4 words
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// Capture WB Block Read - burst of 4 words
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// ======================================
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// ======================================
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always @ ( posedge i_clk )
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always @ ( posedge i_clk )
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if ( i_wb_ready )
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if ( i_wb_cached_ready )
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wb_rdata_burst <= {i_wb_read_data, wb_rdata_burst[127:32]};
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wb_rdata_burst <= i_wb_cached_rdata;
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// ======================================
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// ======================================
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// Miss Address
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// Miss Address
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// ======================================
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// ======================================
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always @ ( posedge i_clk )
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always @ ( posedge i_clk )
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if ( o_wb_req || write_hit )
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if ( o_wb_cached_req || write_hit )
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miss_address <= i_address;
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miss_address <= i_address;
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always @ ( posedge i_clk )
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always @ ( posedge i_clk )
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if ( write_hit )
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if ( write_hit )
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begin
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begin
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| Line 398... |
Line 381... |
c_state == CS_WRITE_HIT1 &&
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c_state == CS_WRITE_HIT1 &&
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request_pulse;
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request_pulse;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ( o_wb_req )
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if ( o_wb_cached_req )
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wb_address <= i_address;
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wb_address <= i_address;
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else if ( i_wb_ready && fill_state )
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else if ( i_wb_cached_ready && fill_state )
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wb_address <= {wb_address[31:4], wb_address[3:2] + 1'd1, 2'd0};
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wb_address <= {wb_address[31:4], wb_address[3:2] + 1'd1, 2'd0};
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assign fill_state = c_state == CS_FILL0 || c_state == CS_FILL1 || c_state == CS_FILL2 || c_state == CS_FILL3 ;
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assign fill_state = c_state == CS_FILL0 || c_state == CS_FILL1 || c_state == CS_FILL2 || c_state == CS_FILL3 ;
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assign wb_hit = i_address == wb_address && i_wb_ready && fill_state;
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assign wb_hit = i_address == wb_address && i_wb_cached_ready && fill_state;
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// ======================================
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// ======================================
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// Hold Requests
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// Hold Requests
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// ======================================
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// ======================================
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| Line 470... |
Line 453... |
// Data comes in off the WB bus in wrap4 with the missed data word first
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// Data comes in off the WB bus in wrap4 with the missed data word first
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assign data_wdata = write_hit && c_state == CS_IDLE ? write_hit_wdata :
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assign data_wdata = write_hit && c_state == CS_IDLE ? write_hit_wdata :
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consecutive_write ? consecutive_write_wdata :
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consecutive_write ? consecutive_write_wdata :
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read_miss_wdata ;
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read_miss_wdata ;
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assign read_miss_wdata = miss_address[3:2] == 2'd0 ? wb_rdata_burst :
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assign read_miss_wdata = wb_rdata_burst;
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miss_address[3:2] == 2'd1 ? { wb_rdata_burst[95:0], wb_rdata_burst[127:96] }:
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miss_address[3:2] == 2'd2 ? { wb_rdata_burst[63:0], wb_rdata_burst[127:64] }:
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{ wb_rdata_burst[31:0], wb_rdata_burst[127:32] };
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assign write_hit_wdata = i_address[3:2] == 2'd0 ? {hit_rdata[127:32], write_data_word } :
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assign write_hit_wdata = i_address[3:2] == 2'd0 ? {hit_rdata[127:32], write_data_word } :
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i_address[3:2] == 2'd1 ? {hit_rdata[127:64], write_data_word, hit_rdata[31:0] } :
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i_address[3:2] == 2'd1 ? {hit_rdata[127:64], write_data_word, hit_rdata[31:0] } :
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i_address[3:2] == 2'd2 ? {hit_rdata[127:96], write_data_word, hit_rdata[63:0] } :
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i_address[3:2] == 2'd2 ? {hit_rdata[127:96], write_data_word, hit_rdata[63:0] } :
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| Line 552... |
Line 532... |
// read miss access to complete. Also for a write idle_hit, need
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// read miss access to complete. Also for a write idle_hit, need
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// to stall for 1 cycle while the data cache is being written to
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// to stall for 1 cycle while the data cache is being written to
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assign write_state = c_state == CS_IDLE || c_state == CS_WRITE_HIT1 ||
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assign write_state = c_state == CS_IDLE || c_state == CS_WRITE_HIT1 ||
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c_state == CS_WRITE_HIT_WAIT_WB || c_state == CS_WRITE_MISS_WAIT_WB;
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c_state == CS_WRITE_HIT_WAIT_WB || c_state == CS_WRITE_MISS_WAIT_WB;
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assign write_stall = (write_miss && !(i_wb_ready && write_state)) || (write_hit && !i_wb_ready);
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assign write_stall = (write_miss && !(i_wb_cached_ready && write_state)) || (write_hit && !i_wb_cached_ready);
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assign read_stall = request_hold && !idle_hit && !rbuf_hit && !wb_hit && !i_write_enable;
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assign read_stall = request_hold && !idle_hit && !rbuf_hit && !wb_hit && !i_write_enable;
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assign cache_busy_stall = c_state == CS_FILL_COMPLETE || c_state == CS_TURN_AROUND || c_state == CS_INIT ||
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assign cache_busy_stall = c_state == CS_FILL_COMPLETE || c_state == CS_TURN_AROUND || c_state == CS_INIT ||
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(fill_state && !rbuf_hit && !wb_hit);
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(fill_state && !rbuf_hit && !wb_hit) ||
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(c_state == CS_WRITE_HIT1 && !consecutive_write);
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// ======================================
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// ======================================
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// Instantiate RAMS
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// Instantiate RAMS
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// ======================================
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// ======================================
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