| Line 123... |
Line 123... |
output [31:0] o_iabt_address,
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output [31:0] o_iabt_address,
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output [7:0] o_iabt_status,
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output [7:0] o_iabt_status,
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output o_dabt_trigger,
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output o_dabt_trigger,
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output [31:0] o_dabt_address,
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output [31:0] o_dabt_address,
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output [7:0] o_dabt_status,
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output [7:0] o_dabt_status,
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output o_conflict
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output o_conflict,
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output reg o_rn_use_read,
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output reg o_rm_use_read,
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output reg o_rs_use_read,
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output reg o_rd_use_read
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);
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);
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`include "a25_localparams.v"
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`include "a25_localparams.v"
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`include "a25_functions.v"
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`include "a25_functions.v"
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| Line 268... |
Line 271... |
reg [31:0] hold_instruction_address = 'd0; // virtual address of abort instruction
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reg [31:0] hold_instruction_address = 'd0; // virtual address of abort instruction
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reg [7:0] hold_instruction_iabt_status = 'd0; // status of abort instruction
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reg [7:0] hold_instruction_iabt_status = 'd0; // status of abort instruction
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wire instruction_valid;
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wire instruction_valid;
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wire instruction_execute;
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wire instruction_execute;
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reg instruction_execute_r = 'd0;
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reg [3:0] mtrans_reg1; // the current register being accessed as part of stm/ldm
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reg [3:0] mtrans_reg1; // the current register being accessed as part of stm/ldm
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reg [3:0] mtrans_reg2; // the next register being accessed as part of stm/ldm
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reg [3:0] mtrans_reg2; // the next register being accessed as part of stm/ldm
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reg [31:0] mtrans_instruction_nxt;
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reg [31:0] mtrans_instruction_nxt;
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wire [15:0] mtrans_reg2_mask;
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wire [15:0] mtrans_reg2_mask;
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| Line 325... |
Line 329... |
wire stm_conflict2b;
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wire stm_conflict2b;
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wire conflict1; // Register conflict1 with ldr operation
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wire conflict1; // Register conflict1 with ldr operation
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wire conflict2; // Register conflict1 with ldr operation
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wire conflict2; // Register conflict1 with ldr operation
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wire conflict; // Register conflict1 with ldr operation
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wire conflict; // Register conflict1 with ldr operation
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reg conflict_r = 'd0;
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reg conflict_r = 'd0;
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reg rn_conflict1_r = 'd0;
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reg rm_conflict1_r = 'd0;
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reg rs_conflict1_r = 'd0;
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reg rd_conflict1_r = 'd0;
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// ========================================================
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// ========================================================
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// Instruction Abort and Data Abort outputs
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// Instruction Abort and Data Abort outputs
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// ========================================================
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// ========================================================
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| Line 513... |
Line 521... |
// Register Conflict Detection
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// Register Conflict Detection
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// ========================================================
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// ========================================================
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assign rn_valid = type == REGOP || type == MULT || type == SWAP || type == TRANS || type == MTRANS || type == CODTRANS;
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assign rn_valid = type == REGOP || type == MULT || type == SWAP || type == TRANS || type == MTRANS || type == CODTRANS;
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assign rm_valid = type == REGOP || type == MULT || type == SWAP || (type == TRANS && immediate_shift_op);
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assign rm_valid = type == REGOP || type == MULT || type == SWAP || (type == TRANS && immediate_shift_op);
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assign rs_valid = rds_use_rs;
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assign rs_valid = rds_use_rs;
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assign rd_valid = type == TRANS && store_op; // str instruction
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assign rd_valid = (type == TRANS && store_op) || (type == REGOP || type == SWAP);
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assign stm_valid = type == MTRANS && !instruction[20]; // stm instruction
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assign stm_valid = type == MTRANS && !instruction[20]; // stm instruction
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assign rn_conflict1 = rn_valid && ( load_rd_d1_nxt[4] && rn_sel_nxt == load_rd_d1_nxt[3:0] );
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assign rn_conflict2 = rn_valid && ( load_rd_d1 [4] && rn_sel_nxt == load_rd_d1 [3:0] );
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assign rn_conflict1 = instruction_execute && rn_valid && ( load_rd_d1_nxt[4] && rn_sel_nxt == load_rd_d1_nxt[3:0] );
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assign rm_conflict1 = rm_valid && ( load_rd_d1_nxt[4] && rm_sel_nxt == load_rd_d1_nxt[3:0] );
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assign rn_conflict2 = instruction_execute_r && rn_valid && ( load_rd_d1 [4] && rn_sel_nxt == load_rd_d1 [3:0] );
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assign rm_conflict2 = rm_valid && ( load_rd_d1 [4] && rm_sel_nxt == load_rd_d1 [3:0] );
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assign rm_conflict1 = instruction_execute && rm_valid && ( load_rd_d1_nxt[4] && rm_sel_nxt == load_rd_d1_nxt[3:0] );
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assign rs_conflict1 = rs_valid && ( load_rd_d1_nxt[4] && rs_sel_nxt == load_rd_d1_nxt[3:0] );
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assign rm_conflict2 = instruction_execute_r && rm_valid && ( load_rd_d1 [4] && rm_sel_nxt == load_rd_d1 [3:0] );
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assign rs_conflict2 = rs_valid && ( load_rd_d1 [4] && rs_sel_nxt == load_rd_d1 [3:0] );
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assign rs_conflict1 = instruction_execute && rs_valid && ( load_rd_d1_nxt[4] && rs_sel_nxt == load_rd_d1_nxt[3:0] );
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assign rd_conflict1 = rd_valid && ( load_rd_d1_nxt[4] && instruction[15:12] == load_rd_d1_nxt[3:0] );
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assign rs_conflict2 = instruction_execute_r && rs_valid && ( load_rd_d1 [4] && rs_sel_nxt == load_rd_d1 [3:0] );
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assign rd_conflict2 = rd_valid && ( load_rd_d1 [4] && instruction[15:12] == load_rd_d1 [3:0] );
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assign rd_conflict1 = instruction_execute && rd_valid && ( load_rd_d1_nxt[4] && instruction[15:12] == load_rd_d1_nxt[3:0] );
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assign stm_conflict1a = stm_valid && ( load_rd_d1_nxt[4] && mtrans_reg1 == load_rd_d1_nxt[3:0] );
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assign rd_conflict2 = instruction_execute_r && rd_valid && ( load_rd_d1 [4] && instruction[15:12] == load_rd_d1 [3:0] );
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assign stm_conflict1b = stm_valid && ( load_rd_d1_nxt[4] && mtrans_reg2 == load_rd_d1_nxt[3:0] );
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assign stm_conflict2a = stm_valid && ( load_rd_d1 [4] && mtrans_reg1 == load_rd_d1 [3:0] );
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assign stm_conflict1a = instruction_execute && stm_valid && ( load_rd_d1_nxt[4] && mtrans_reg1 == load_rd_d1_nxt[3:0] );
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assign stm_conflict2b = stm_valid && ( load_rd_d1 [4] && mtrans_reg2 == load_rd_d1 [3:0] );
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assign stm_conflict1b = instruction_execute && stm_valid && ( load_rd_d1_nxt[4] && mtrans_reg2 == load_rd_d1_nxt[3:0] );
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assign stm_conflict2a = instruction_execute_r && stm_valid && ( load_rd_d1 [4] && mtrans_reg1 == load_rd_d1 [3:0] );
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assign stm_conflict2b = instruction_execute_r && stm_valid && ( load_rd_d1 [4] && mtrans_reg2 == load_rd_d1 [3:0] );
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assign conflict1 = instruction_valid &&
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assign conflict1 = instruction_valid &&
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(rn_conflict1 || rm_conflict1 || rs_conflict1 || rd_conflict1 ||
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(rn_conflict1 || rm_conflict1 || rs_conflict1 || rd_conflict1 ||
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stm_conflict1a || stm_conflict1b);
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stm_conflict1a || stm_conflict1b);
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assign conflict2 = instruction_valid &&
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assign conflict2 = instruction_valid && (stm_conflict2a || stm_conflict2b);
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(rn_conflict2 || rm_conflict2 || rs_conflict2 || rd_conflict2 ||
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stm_conflict2a || stm_conflict2b);
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assign conflict = conflict1 || conflict2;
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assign conflict = conflict1 || conflict2;
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always @( posedge i_clk )
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always @( posedge i_clk )
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if ( !i_access_stall )
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if ( !i_access_stall )
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begin
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begin
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conflict_r <= conflict;
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conflict_r <= conflict;
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instruction_execute_r <= instruction_execute;
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rn_conflict1_r <= rn_conflict1 && instruction_execute;
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rm_conflict1_r <= rm_conflict1 && instruction_execute;
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rs_conflict1_r <= rs_conflict1 && instruction_execute;
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rd_conflict1_r <= rd_conflict1 && instruction_execute;
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o_rn_use_read <= instruction_valid && ( rn_conflict1_r || rn_conflict2 );
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o_rm_use_read <= instruction_valid && ( rm_conflict1_r || rm_conflict2 );
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o_rs_use_read <= instruction_valid && ( rs_conflict1_r || rs_conflict2 );
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o_rd_use_read <= instruction_valid && ( rd_conflict1_r || rd_conflict2 );
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end
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end
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assign o_conflict = conflict;
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assign o_conflict = conflict;
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