| Line 117... |
Line 117... |
input i_status_bits_flags_wen,
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input i_status_bits_flags_wen,
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input i_status_bits_mode_wen,
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input i_status_bits_mode_wen,
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input i_status_bits_irq_mask_wen,
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input i_status_bits_irq_mask_wen,
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input i_status_bits_firq_mask_wen,
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input i_status_bits_firq_mask_wen,
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input i_copro_write_data_wen,
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input i_copro_write_data_wen,
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input i_conflict
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input i_conflict,
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input i_rn_use_read,
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input i_rm_use_read,
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input i_rs_use_read,
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input i_rd_use_read
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);
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);
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`include "a25_localparams.v"
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`include "a25_localparams.v"
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`include "a25_functions.v"
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`include "a25_functions.v"
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| Line 140... |
Line 143... |
wire [3:0] alu_flags;
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wire [3:0] alu_flags;
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wire [31:0] rm;
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wire [31:0] rm;
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wire [31:0] rs;
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wire [31:0] rs;
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wire [31:0] rd;
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wire [31:0] rd;
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wire [31:0] rn;
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wire [31:0] rn;
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wire [31:0] reg_bank_rn;
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wire [31:0] reg_bank_rm;
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wire [31:0] reg_bank_rs;
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wire [31:0] reg_bank_rd;
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wire [31:0] pc;
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wire [31:0] pc;
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wire [31:0] pc_nxt;
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wire [31:0] pc_nxt;
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wire [31:0] interrupt_vector;
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wire [31:0] interrupt_vector;
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wire [7:0] shift_amount;
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wire [7:0] shift_amount;
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wire [31:0] barrel_shift_in;
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wire [31:0] barrel_shift_in;
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| Line 171... |
Line 178... |
wire [1:0] multiply_flags;
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wire [1:0] multiply_flags;
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reg [31:0] base_address = 'd0; // Saves base address during LDM instruction in
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reg [31:0] base_address = 'd0; // Saves base address during LDM instruction in
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// case of data abort
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// case of data abort
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wire [31:0] read_data_filtered1;
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wire [31:0] read_data_filtered1;
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wire [31:0] read_data_filtered;
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wire [31:0] read_data_filtered;
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wire [31:0] read_data_filtered_c;
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reg [31:0] read_data_filtered_r = 'd0;
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reg [3:0] load_rd_r = 'd0;
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wire [3:0] load_rd_c;
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wire write_enable_nxt;
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wire write_enable_nxt;
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wire daddress_valid_nxt;
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wire daddress_valid_nxt;
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wire iaddress_valid_nxt;
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wire iaddress_valid_nxt;
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wire priviledged_nxt;
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wire priviledged_nxt;
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| Line 444... |
Line 455... |
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// ========================================================
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// ========================================================
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// Address Valid
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// Address Valid
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// ========================================================
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// ========================================================
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assign daddress_valid_nxt = execute && i_decode_daccess && !i_access_stall;
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assign daddress_valid_nxt = execute && i_decode_daccess && !i_access_stall;
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assign iaddress_valid_nxt = i_decode_iaccess;
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// For some multi-cycle instructions, the stream of instrution
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// reads can be paused. However if the instruction does not execute
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// then the read stream must not be interrupted.
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assign iaddress_valid_nxt = i_decode_iaccess || !execute;
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// ========================================================
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// Use read value from data memory instead of from register
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// ========================================================
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assign rn = i_rn_use_read && i_rn_sel == load_rd_c ? read_data_filtered_c : reg_bank_rn;
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assign rm = i_rm_use_read && i_rm_sel == load_rd_c ? read_data_filtered_c : reg_bank_rm;
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assign rs = i_rs_use_read && i_rs_sel == load_rd_c ? read_data_filtered_c : reg_bank_rs;
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assign rd = i_rd_use_read && i_rs_sel == load_rd_c ? read_data_filtered_c : reg_bank_rd;
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always@( posedge i_clk )
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if ( i_wb_read_data_valid )
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begin
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read_data_filtered_r <= read_data_filtered;
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load_rd_r <= i_wb_load_rd[3:0];
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end
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assign read_data_filtered_c = i_wb_read_data_valid ? read_data_filtered : read_data_filtered_r;
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assign load_rd_c = i_wb_read_data_valid ? i_wb_load_rd[3:0] : load_rd_r;
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// ========================================================
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// ========================================================
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// Register Update
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// Register Update
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// ========================================================
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// ========================================================
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| Line 574... |
Line 609... |
.i_firq_not_user_mode ( i_firq_not_user_mode ),
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.i_firq_not_user_mode ( i_firq_not_user_mode ),
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// use one-hot version for speed, combine with i_user_mode_regs_store
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// use one-hot version for speed, combine with i_user_mode_regs_store
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.i_mode_rds_exec ( status_bits_mode_rds_oh ),
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.i_mode_rds_exec ( status_bits_mode_rds_oh ),
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.o_rm ( rm ),
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.o_rm ( reg_bank_rm ),
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.o_rs ( rs ),
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.o_rs ( reg_bank_rs ),
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.o_rd ( rd ),
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.o_rd ( reg_bank_rd ),
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.o_rn ( rn ),
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.o_rn ( reg_bank_rn ),
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.o_pc ( pc )
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.o_pc ( pc )
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);
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);
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// ========================================================
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// ========================================================
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// Debug - non-synthesizable code
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// Debug - non-synthesizable code
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// ========================================================
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// ========================================================
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//synopsys translate_off
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//synopsys translate_off
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