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module a25_execute (
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module a25_execute (
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input i_clk,
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input i_clk,
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input i_access_stall, // stall all stages of the cpu at the same time
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input i_core_stall, // stall all stages of the Amber core at the same time
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input i_mem_stall, // data memory access stalls
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input i_mem_stall, // data memory access stalls
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output o_exec_stall, // stall the core pipeline
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input [31:0] i_wb_read_data, // data reads
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input [31:0] i_wb_read_data, // data reads
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input i_wb_read_data_valid, // read data is valid
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input i_wb_read_data_valid, // read data is valid
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input [9:0] i_wb_load_rd, // Rd for data reads
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input [10:0] i_wb_load_rd, // Rd for data reads
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input [31:0] i_copro_read_data, // From Co-Processor, to either Register
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input [31:0] i_copro_read_data, // From Co-Processor, to either Register
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// or Memory
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// or Memory
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input i_decode_iaccess, // Indicates an instruction access
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input i_decode_iaccess, // Indicates an instruction access
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input i_decode_daccess, // Indicates a data access
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input i_decode_daccess, // Indicates a data access
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| Line 71... |
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output reg o_adex = 'd0, // Address Exception
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output reg o_adex = 'd0, // Address Exception
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output reg o_priviledged = 'd0, // Priviledged access
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output reg o_priviledged = 'd0, // Priviledged access
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output reg o_exclusive = 'd0, // swap access
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output reg o_exclusive = 'd0, // swap access
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output reg o_write_enable = 'd0,
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output reg o_write_enable = 'd0,
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output reg [3:0] o_byte_enable = 'd0,
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output reg [3:0] o_byte_enable = 'd0,
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output reg [7:0] o_exec_load_rd = 'd0, // The destination register for a load instruction
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output reg [8:0] o_exec_load_rd = 'd0, // The destination register for a load instruction
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output [31:0] o_status_bits, // Full PC will all status bits, but PC part zero'ed out
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output [31:0] o_status_bits, // Full PC will all status bits, but PC part zero'ed out
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output o_multiply_done,
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output o_multiply_done,
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// --------------------------------------------------
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// --------------------------------------------------
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wire [31:0] interrupt_vector;
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wire [31:0] interrupt_vector;
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wire [7:0] shift_amount;
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wire [7:0] shift_amount;
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wire [31:0] barrel_shift_in;
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wire [31:0] barrel_shift_in;
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wire [31:0] barrel_shift_out;
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wire [31:0] barrel_shift_out;
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wire barrel_shift_carry;
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wire barrel_shift_carry;
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wire barrel_shift_stall;
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wire [3:0] status_bits_flags_nxt;
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wire [3:0] status_bits_flags_nxt;
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reg [3:0] status_bits_flags = 'd0;
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reg [3:0] status_bits_flags = 'd0;
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wire [1:0] status_bits_mode_nxt;
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wire [1:0] status_bits_mode_nxt;
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reg [1:0] status_bits_mode = SVC;
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reg [1:0] status_bits_mode = SVC;
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wire status_bits_mode_rds_oh_update;
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wire status_bits_mode_rds_oh_update;
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wire status_bits_irq_mask_nxt;
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wire status_bits_irq_mask_nxt;
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reg status_bits_irq_mask = 1'd1;
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reg status_bits_irq_mask = 1'd1;
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wire status_bits_firq_mask_nxt;
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wire status_bits_firq_mask_nxt;
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reg status_bits_firq_mask = 1'd1;
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reg status_bits_firq_mask = 1'd1;
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wire [8:0] exec_load_rd_nxt;
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wire execute; // high when condition execution is true
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wire execute; // high when condition execution is true
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wire [31:0] reg_write_nxt;
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wire [31:0] reg_write_nxt;
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wire pc_wen;
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wire pc_wen;
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wire [14:0] reg_bank_wen;
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wire [14:0] reg_bank_wen;
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// ========================================================
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// ========================================================
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// Status Bits Select
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// Status Bits Select
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// ========================================================
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// ========================================================
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assign ldm_flags = i_wb_read_data_valid & ~i_mem_stall & i_wb_load_rd[7];
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assign ldm_flags = i_wb_read_data_valid & ~i_mem_stall & i_wb_load_rd[8];
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assign ldm_status_bits = i_wb_read_data_valid & ~i_mem_stall & i_wb_load_rd[6];
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assign ldm_status_bits = i_wb_read_data_valid & ~i_mem_stall & i_wb_load_rd[7];
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assign status_bits_flags_nxt = ldm_flags ? read_data_filtered[31:28] :
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assign status_bits_flags_nxt = ldm_flags ? read_data_filtered[31:28] :
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i_status_bits_sel == 3'd0 ? alu_flags :
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i_status_bits_sel == 3'd0 ? alu_flags :
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i_status_bits_sel == 3'd1 ? alu_out [31:28] :
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i_status_bits_sel == 3'd1 ? alu_out [31:28] :
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Line 349... |
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// ========================================================
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// ========================================================
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// Filter Read Data
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// Filter Read Data
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// ========================================================
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// ========================================================
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// mem_load_rd[9:8] -> shift ROR bytes
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// mem_load_rd[10:9]-> shift ROR bytes
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// mem_load_rd[7] -> load flags with PC
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// mem_load_rd[8] -> load flags with PC
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// mem_load_rd[6] -> load status bits with PC
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// mem_load_rd[7] -> load status bits with PC
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// mem_load_rd[5] -> Write into User Mode register
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// mem_load_rd[6:5] -> Write into this Mode registers
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// mem_load_rd[4] -> zero_extend byte
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// mem_load_rd[4] -> zero_extend byte
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// mem_load_rd[3:0] -> Destination Register
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// mem_load_rd[3:0] -> Destination Register
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assign read_data_filtered1 = i_wb_load_rd[9:8] === 2'd0 ? i_wb_read_data :
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assign read_data_filtered1 = i_wb_load_rd[10:9] === 2'd0 ? i_wb_read_data :
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i_wb_load_rd[9:8] === 2'd1 ? {i_wb_read_data[7:0], i_wb_read_data[31:8]} :
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i_wb_load_rd[10:9] === 2'd1 ? {i_wb_read_data[7:0], i_wb_read_data[31:8]} :
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i_wb_load_rd[9:8] === 2'd2 ? {i_wb_read_data[15:0], i_wb_read_data[31:16]} :
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i_wb_load_rd[10:9] === 2'd2 ? {i_wb_read_data[15:0], i_wb_read_data[31:16]} :
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{i_wb_read_data[23:0], i_wb_read_data[31:24]} ;
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{i_wb_read_data[23:0], i_wb_read_data[31:24]} ;
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assign read_data_filtered = i_wb_load_rd[4] ? {24'd0, read_data_filtered1[7:0]} : read_data_filtered1 ;
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assign read_data_filtered = i_wb_load_rd[4] ? {24'd0, read_data_filtered1[7:0]} : read_data_filtered1 ;
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// ========================================================
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// ========================================================
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// Address Valid
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// Address Valid
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// ========================================================
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// ========================================================
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assign daddress_valid_nxt = execute && i_decode_daccess && !i_access_stall;
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assign daddress_valid_nxt = execute && i_decode_daccess && !i_core_stall;
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// For some multi-cycle instructions, the stream of instrution
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// For some multi-cycle instructions, the stream of instrution
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// reads can be paused. However if the instruction does not execute
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// reads can be paused. However if the instruction does not execute
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// then the read stream must not be interrupted.
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// then the read stream must not be interrupted.
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assign iaddress_valid_nxt = i_decode_iaccess || !execute;
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assign iaddress_valid_nxt = i_decode_iaccess || !execute;
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assign read_data_filtered_c = i_wb_read_data_valid ? read_data_filtered : read_data_filtered_r;
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assign read_data_filtered_c = i_wb_read_data_valid ? read_data_filtered : read_data_filtered_r;
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assign load_rd_c = i_wb_read_data_valid ? i_wb_load_rd[3:0] : load_rd_r;
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assign load_rd_c = i_wb_read_data_valid ? i_wb_load_rd[3:0] : load_rd_r;
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// ========================================================
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// ========================================================
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// Set mode for the destination registers of a mem read
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// ========================================================
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// The mode is either user mode, or the current mode
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assign exec_load_rd_nxt = { i_decode_load_rd[7:6],
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i_decode_load_rd[5] ? USR : status_bits_mode, // 1 bit -> 2 bits
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i_decode_load_rd[4:0] };
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// ========================================================
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// Register Update
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// Register Update
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// ========================================================
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// ========================================================
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assign o_exec_stall = barrel_shift_stall;
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assign daddress_update = !i_access_stall;
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assign daddress_update = !i_core_stall;
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assign exec_load_rd_update = !i_access_stall && execute;
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assign exec_load_rd_update = !i_core_stall && execute;
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assign priviledged_update = !i_access_stall;
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assign priviledged_update = !i_core_stall;
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assign exclusive_update = !i_access_stall && execute;
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assign exclusive_update = !i_core_stall && execute;
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assign write_enable_update = !i_access_stall;
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assign write_enable_update = !i_core_stall;
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assign write_data_update = !i_access_stall && execute && i_write_data_wen;
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assign write_data_update = !i_core_stall && execute && i_write_data_wen;
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assign byte_enable_update = !i_access_stall && execute && i_write_data_wen;
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assign byte_enable_update = !i_core_stall && execute && i_write_data_wen;
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assign iaddress_update = pc_dmem_wen || (!i_access_stall && !i_conflict);
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assign iaddress_update = pc_dmem_wen || (!i_core_stall && !i_conflict);
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assign copro_write_data_update = !i_access_stall && execute && i_copro_write_data_wen;
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assign copro_write_data_update = !i_core_stall && execute && i_copro_write_data_wen;
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assign base_address_update = !i_access_stall && execute && i_base_address_wen;
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assign base_address_update = !i_core_stall && execute && i_base_address_wen;
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// assign dcache_read_data_update = !i_mem_stall;
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assign status_bits_flags_update = ldm_flags || (!i_core_stall && execute && i_status_bits_flags_wen);
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assign status_bits_flags_update = ldm_flags || (!i_access_stall && execute && i_status_bits_flags_wen);
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assign status_bits_mode_update = ldm_status_bits || (!i_core_stall && execute && i_status_bits_mode_wen);
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assign status_bits_mode_update = ldm_status_bits || (!i_access_stall && execute && i_status_bits_mode_wen);
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assign status_bits_mode_rds_oh_update = !i_core_stall;
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assign status_bits_mode_rds_oh_update = !i_access_stall;
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assign status_bits_irq_mask_update = ldm_status_bits || (!i_core_stall && execute && i_status_bits_irq_mask_wen);
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assign status_bits_irq_mask_update = ldm_status_bits || (!i_access_stall && execute && i_status_bits_irq_mask_wen);
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assign status_bits_firq_mask_update = ldm_status_bits || (!i_core_stall && execute && i_status_bits_firq_mask_wen);
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assign status_bits_firq_mask_update = ldm_status_bits || (!i_access_stall && execute && i_status_bits_firq_mask_wen);
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always @( posedge i_clk )
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always @( posedge i_clk )
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begin
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begin
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o_daddress <= daddress_update ? o_daddress_nxt : o_daddress;
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o_daddress <= daddress_update ? o_daddress_nxt : o_daddress;
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o_daddress_valid <= daddress_update ? daddress_valid_nxt : o_daddress_valid;
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o_daddress_valid <= daddress_update ? daddress_valid_nxt : o_daddress_valid;
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o_exec_load_rd <= exec_load_rd_update ? i_decode_load_rd : o_exec_load_rd;
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o_exec_load_rd <= exec_load_rd_update ? exec_load_rd_nxt : o_exec_load_rd;
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o_priviledged <= priviledged_update ? priviledged_nxt : o_priviledged;
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o_priviledged <= priviledged_update ? priviledged_nxt : o_priviledged;
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o_exclusive <= exclusive_update ? i_decode_exclusive : o_exclusive;
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o_exclusive <= exclusive_update ? i_decode_exclusive : o_exclusive;
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o_write_enable <= write_enable_update ? write_enable_nxt : o_write_enable;
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o_write_enable <= write_enable_update ? write_enable_nxt : o_write_enable;
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o_write_data <= write_data_update ? write_data_nxt : o_write_data;
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o_write_data <= write_data_update ? write_data_nxt : o_write_data;
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o_byte_enable <= byte_enable_update ? byte_enable_nxt : o_byte_enable;
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o_byte_enable <= byte_enable_update ? byte_enable_nxt : o_byte_enable;
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| Line 535... |
Line 547... |
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// ========================================================
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// ========================================================
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// Instantiate Barrel Shift
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// Instantiate Barrel Shift
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// ========================================================
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// ========================================================
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a25_barrel_shift u_barrel_shift (
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a25_barrel_shift u_barrel_shift (
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.i_clk ( i_clk ),
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.i_in ( barrel_shift_in ),
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.i_in ( barrel_shift_in ),
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.i_carry_in ( status_bits_flags[1] ),
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.i_carry_in ( status_bits_flags[1] ),
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.i_shift_amount ( shift_amount ),
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.i_shift_amount ( shift_amount ),
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.i_shift_imm_zero ( i_shift_imm_zero ),
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.i_shift_imm_zero ( i_shift_imm_zero ),
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.i_function ( i_barrel_shift_function ),
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.i_function ( i_barrel_shift_function ),
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.o_out ( barrel_shift_out ),
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.o_out ( barrel_shift_out ),
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.o_carry_out ( barrel_shift_carry )
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.o_carry_out ( barrel_shift_carry ),
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.o_stall ( barrel_shift_stall )
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);
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);
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// ========================================================
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// ========================================================
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// Instantiate ALU
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// Instantiate ALU
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Line 580... |
// ========================================================
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// ========================================================
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// Instantiate Booth 64-bit Multiplier-Accumulator
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// Instantiate Booth 64-bit Multiplier-Accumulator
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// ========================================================
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// ========================================================
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a25_multiply u_multiply (
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a25_multiply u_multiply (
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.i_clk ( i_clk ),
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.i_clk ( i_clk ),
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.i_access_stall ( i_access_stall ),
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.i_core_stall ( i_core_stall ),
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.i_a_in ( rs ),
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.i_a_in ( rs ),
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.i_b_in ( rm ),
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.i_b_in ( rm ),
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.i_function ( i_multiply_function ),
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.i_function ( i_multiply_function ),
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.i_execute ( execute ),
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.i_execute ( execute ),
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.o_out ( multiply_out ),
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.o_out ( multiply_out ),
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| Line 582... |
Line 596... |
// ========================================================
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// ========================================================
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// Instantiate Register Bank
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// Instantiate Register Bank
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// ========================================================
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// ========================================================
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a25_register_bank u_register_bank(
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a25_register_bank u_register_bank(
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.i_clk ( i_clk ),
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.i_clk ( i_clk ),
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.i_access_stall ( i_access_stall ),
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.i_core_stall ( i_core_stall ),
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.i_mem_stall ( i_mem_stall ),
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.i_mem_stall ( i_mem_stall ),
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.i_rm_sel ( i_rm_sel ),
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.i_rm_sel ( i_rm_sel ),
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.i_rs_sel ( i_rs_sel ),
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.i_rs_sel ( i_rs_sel ),
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.i_rn_sel ( i_rn_sel ),
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.i_rn_sel ( i_rn_sel ),
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.i_pc_wen ( pc_wen ),
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.i_pc_wen ( pc_wen ),
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| Line 597... |
Line 611... |
.i_mode_exec ( status_bits_mode ),
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.i_mode_exec ( status_bits_mode ),
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.i_wb_read_data ( read_data_filtered ),
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.i_wb_read_data ( read_data_filtered ),
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.i_wb_read_data_valid ( i_wb_read_data_valid ),
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.i_wb_read_data_valid ( i_wb_read_data_valid ),
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.i_wb_read_data_rd ( i_wb_load_rd[3:0] ),
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.i_wb_read_data_rd ( i_wb_load_rd[3:0] ),
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.i_wb_user_mode ( i_wb_load_rd[5] ),
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.i_wb_mode ( i_wb_load_rd[6:5] ),
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.i_status_bits_flags ( status_bits_flags ),
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.i_status_bits_flags ( status_bits_flags ),
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.i_status_bits_irq_mask ( status_bits_irq_mask ),
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.i_status_bits_irq_mask ( status_bits_irq_mask ),
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.i_status_bits_firq_mask ( status_bits_firq_mask ),
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.i_status_bits_firq_mask ( status_bits_firq_mask ),
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