//////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////
|
// //
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// //
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// Wishbone master interface for the Amber 25 core //
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// Wishbone master interface for the Amber 25 core //
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// //
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// //
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// This file is part of the Amber project //
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// This file is part of the Amber project //
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// http://www.opencores.org/project,amber //
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// http://www.opencores.org/project,amber //
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// //
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// //
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// Description //
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// Description //
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// Turns memory access requests from the execute stage and //
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// Turns memory access requests from the execute stage and //
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// cache into wishbone bus cycles. For 4-word read requests //
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// instruction and data caches into wishbone bus cycles. //
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// from the cache and swap accesses ( read followed by write //
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// For 4-word read requests from either cache and swap //
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// to the same address) from the execute stage, //
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// accesses ( read followed by write to the same address) //
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// a block transfer is done. All other requests result in //
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// from the execute stage, a block transfer is done. //
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// single word transfers. //
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// All other requests result in single word transfers. //
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// //
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// //
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// Write accesses can be done in a single clock cycle on //
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// Write accesses can be done in a single clock cycle on //
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// the wishbone bus, is the destination allows it. The //
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// the wishbone bus, is the destination allows it. The //
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// next transfer will begin immediately on the //
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// next transfer will begin immediately on the //
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// next cycle on the bus. This looks like a block transfer //
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// next cycle on the bus. This looks like a block transfer //
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// and does hold ownership of the wishbone bus, preventing //
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// and does hold ownership of the wishbone bus, preventing //
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// the other master ( the ethernet MAC) from gaining //
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// the other master ( the ethernet MAC) from gaining //
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// ownership between those two cycles. But otherwise it would //
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// ownership between those two cycles. But otherwise it would //
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// be necessary to insert a wait cycle after every write, //
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// be necessary to insert a wait cycle after every write, //
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// slowing down the performance of the core by around 5 to //
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// slowing down the performance of the core by around 5 to //
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// 10%. //
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// 10%. //
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// //
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// //
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// Author(s): //
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// Author(s): //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// //
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// //
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//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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// //
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// //
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// Copyright (C) 2011 Authors and OPENCORES.ORG //
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// Copyright (C) 2011 Authors and OPENCORES.ORG //
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// //
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// //
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// This source file may be used and distributed without //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// removed from the file and that any derivative work contains //
|
// the original copyright notice and the associated disclaimer. //
|
// the original copyright notice and the associated disclaimer. //
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// //
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// //
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// This source file is free software; you can redistribute it //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// later version. //
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// //
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// //
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// This source is distributed in the hope that it will be //
|
// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// details. //
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// //
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// //
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// You should have received a copy of the GNU Lesser General //
|
// You should have received a copy of the GNU Lesser General //
|
// Public License along with this source; if not, download it //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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// //
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//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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module a25_wishbone
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module a25_wishbone
|
(
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(
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input i_clk,
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input i_clk,
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|
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// Instruction Cache Accesses
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// Instruction Cache Accesses
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input i_icache_req,
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input i_icache_req,
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input i_icache_qword,
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input i_icache_qword,
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input [31:0] i_icache_address,
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input [31:0] i_icache_address,
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output [31:0] o_icache_read_data,
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output [31:0] o_icache_read_data,
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output o_icache_ready,
|
output o_icache_ready,
|
|
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// Data Cache Accesses
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// Data Cache Accesses
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input i_exclusive, // high for read part of swap access
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input i_exclusive, // high for read part of swap access
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input i_dcache_cached_req,
|
input i_dcache_cached_req,
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input i_dcache_uncached_req,
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input i_dcache_uncached_req,
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input i_dcache_qword,
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input i_dcache_qword,
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input i_dcache_write,
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input i_dcache_write,
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input [31:0] i_dcache_write_data,
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input [31:0] i_dcache_write_data,
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input [3:0] i_dcache_byte_enable, // valid for writes only
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input [3:0] i_dcache_byte_enable, // valid for writes only
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input [31:0] i_dcache_address,
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input [31:0] i_dcache_address,
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output [31:0] o_dcache_read_data,
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output [31:0] o_dcache_read_data,
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output o_dcache_cached_ready,
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output o_dcache_cached_ready,
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output o_dcache_uncached_ready,
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output o_dcache_uncached_ready,
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|
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// Wishbone Bus
|
// Wishbone Bus
|
output reg [31:0] o_wb_adr = 'd0,
|
output reg [31:0] o_wb_adr = 'd0,
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output reg [3:0] o_wb_sel = 'd0,
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output reg [3:0] o_wb_sel = 'd0,
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output reg o_wb_we = 'd0,
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output reg o_wb_we = 'd0,
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input [31:0] i_wb_dat,
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input [31:0] i_wb_dat,
|
output reg [31:0] o_wb_dat = 'd0,
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output reg [31:0] o_wb_dat = 'd0,
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output reg o_wb_cyc = 'd0,
|
output reg o_wb_cyc = 'd0,
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output reg o_wb_stb = 'd0,
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output reg o_wb_stb = 'd0,
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input i_wb_ack,
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input i_wb_ack,
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input i_wb_err
|
input i_wb_err
|
|
|
);
|
);
|
|
|
|
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localparam [3:0] WB_IDLE = 3'd0,
|
localparam [3:0] WB_IDLE = 3'd0,
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WB_BURST1 = 3'd1,
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WB_BURST1 = 3'd1,
|
WB_BURST2 = 3'd2,
|
WB_BURST2 = 3'd2,
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WB_BURST3 = 3'd3,
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WB_BURST3 = 3'd3,
|
WB_WAIT_ACK = 3'd4;
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WB_WAIT_ACK = 3'd4;
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|
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reg [2:0] wishbone_st = WB_IDLE;
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reg [2:0] wishbone_st = WB_IDLE;
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|
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wire icache_read_req_c;
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wire icache_read_req_c;
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wire icache_read_qword_c;
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wire icache_read_qword_c;
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wire [31:0] icache_read_addr_c;
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wire [31:0] icache_read_addr_c;
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wire dcache_read_qword_c;
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wire dcache_read_qword_c;
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|
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wire dcache_req_c;
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wire dcache_req_c;
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wire write_req_c;
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wire write_req_c;
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wire dcache_cached_rreq_c;
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wire dcache_cached_rreq_c;
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wire dcache_cached_wreq_c;
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wire dcache_cached_wreq_c;
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wire dcache_uncached_rreq_c;
|
wire dcache_uncached_rreq_c;
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wire dcache_uncached_wreq_c;
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wire dcache_uncached_wreq_c;
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|
|
wire dcache_cached_rreq_in;
|
wire dcache_cached_rreq_in;
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wire dcache_cached_wreq_in;
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wire dcache_cached_wreq_in;
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wire dcache_uncached_rreq_in;
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wire dcache_uncached_rreq_in;
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wire dcache_uncached_wreq_in;
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wire dcache_uncached_wreq_in;
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|
|
reg dcache_cached_rreq_r = 'd0;
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reg dcache_cached_rreq_r = 'd0;
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reg dcache_cached_wreq_r = 'd0;
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reg dcache_cached_wreq_r = 'd0;
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reg dcache_uncached_rreq_r = 'd0;
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reg dcache_uncached_rreq_r = 'd0;
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reg dcache_uncached_wreq_r = 'd0;
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reg dcache_uncached_wreq_r = 'd0;
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|
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wire dcache_cached_wready;
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wire dcache_cached_wready;
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wire dcache_uncached_wready;
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wire dcache_uncached_wready;
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wire dcache_cached_rready;
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wire dcache_cached_rready;
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wire dcache_uncached_rready;
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wire dcache_uncached_rready;
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|
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wire start_access;
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wire start_access;
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wire [3:0] byte_enable;
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wire [3:0] byte_enable;
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reg exclusive_access = 'd0;
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reg exclusive_access = 'd0;
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wire read_ack;
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wire read_ack;
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wire wait_write_ack;
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wire wait_write_ack;
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reg icache_read_req_r = 'd0;
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reg icache_read_req_r = 'd0;
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reg icache_read_qword_r = 'd0;
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reg icache_read_qword_r = 'd0;
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reg [31:0] icache_read_addr_r = 'd0;
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reg [31:0] icache_read_addr_r = 'd0;
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reg dcache_read_qword_r = 'd0;
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reg dcache_read_qword_r = 'd0;
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wire icache_read_req_in;
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wire icache_read_req_in;
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wire icache_read_ready;
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wire icache_read_ready;
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reg servicing_dcache_cached_read_r = 'd0;
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reg servicing_dcache_cached_read_r = 'd0;
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reg servicing_dcache_uncached_read_r = 'd0;
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reg servicing_dcache_uncached_read_r = 'd0;
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reg servicing_icache_r = 'd0;
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reg servicing_icache_r = 'd0;
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wire extra_write;
|
wire extra_write;
|
reg extra_write_r = 'd0;
|
reg extra_write_r = 'd0;
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reg [31:0] extra_write_data_r;
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reg [31:0] extra_write_data_r;
|
reg [31:0] extra_write_address_r;
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reg [31:0] extra_write_address_r;
|
reg [3:0] extra_write_be_r;
|
reg [3:0] extra_write_be_r;
|
|
|
assign read_ack = !o_wb_we && i_wb_ack;
|
assign read_ack = !o_wb_we && i_wb_ack;
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|
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assign dcache_cached_rready = dcache_cached_rreq_r && servicing_dcache_cached_read_r && read_ack;
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assign dcache_cached_rready = dcache_cached_rreq_r && servicing_dcache_cached_read_r && read_ack;
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assign dcache_uncached_rready = dcache_uncached_rreq_r && servicing_dcache_uncached_read_r && read_ack;
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assign dcache_uncached_rready = dcache_uncached_rreq_r && servicing_dcache_uncached_read_r && read_ack;
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|
|
|
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assign o_dcache_cached_ready = dcache_cached_rready || dcache_cached_wready;
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assign o_dcache_cached_ready = dcache_cached_rready || dcache_cached_wready;
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assign o_dcache_uncached_ready = dcache_uncached_rready || dcache_uncached_wready;
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assign o_dcache_uncached_ready = dcache_uncached_rready || dcache_uncached_wready;
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assign o_dcache_read_data = i_wb_dat;
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assign o_dcache_read_data = i_wb_dat;
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|
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assign icache_read_ready = servicing_icache_r && read_ack;
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assign icache_read_ready = servicing_icache_r && read_ack;
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assign o_icache_ready = icache_read_ready;
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assign o_icache_ready = icache_read_ready;
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assign o_icache_read_data = i_wb_dat;
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assign o_icache_read_data = i_wb_dat;
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|
|
|
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assign dcache_cached_rreq_in = i_dcache_cached_req && !i_dcache_write;
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assign dcache_cached_rreq_in = i_dcache_cached_req && !i_dcache_write;
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assign dcache_cached_wreq_in = i_dcache_cached_req && i_dcache_write;
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assign dcache_cached_wreq_in = i_dcache_cached_req && i_dcache_write;
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assign dcache_uncached_rreq_in = i_dcache_uncached_req && !i_dcache_write;
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assign dcache_uncached_rreq_in = i_dcache_uncached_req && !i_dcache_write;
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assign dcache_uncached_wreq_in = i_dcache_uncached_req && i_dcache_write;
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assign dcache_uncached_wreq_in = i_dcache_uncached_req && i_dcache_write;
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assign icache_read_req_in = i_icache_req && !o_icache_ready;
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assign icache_read_req_in = i_icache_req && !o_icache_ready;
|
|
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assign dcache_cached_rreq_c = ( dcache_cached_rreq_in || dcache_cached_rreq_r ) && !(servicing_dcache_cached_read_r && read_ack);
|
assign dcache_cached_rreq_c = ( dcache_cached_rreq_in || dcache_cached_rreq_r ) && !(servicing_dcache_cached_read_r && read_ack);
|
assign dcache_uncached_rreq_c = ( dcache_uncached_rreq_in || dcache_uncached_rreq_r ) && !(servicing_dcache_uncached_read_r && read_ack);
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assign dcache_uncached_rreq_c = ( dcache_uncached_rreq_in || dcache_uncached_rreq_r ) && !(servicing_dcache_uncached_read_r && read_ack);
|
|
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assign dcache_read_qword_c = ( i_dcache_qword || dcache_read_qword_r ) && !(servicing_dcache_cached_read_r && read_ack);
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assign dcache_read_qword_c = ( i_dcache_qword || dcache_read_qword_r ) && !(servicing_dcache_cached_read_r && read_ack);
|
|
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assign icache_read_req_c = ( icache_read_req_in || icache_read_req_r ) && !(servicing_icache_r && read_ack);
|
assign icache_read_req_c = ( icache_read_req_in || icache_read_req_r ) && !(servicing_icache_r && read_ack);
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assign icache_read_qword_c = ( i_icache_qword || icache_read_qword_r ) && !(servicing_icache_r && read_ack);
|
assign icache_read_qword_c = ( i_icache_qword || icache_read_qword_r ) && !(servicing_icache_r && read_ack);
|
assign icache_read_addr_c = i_icache_req ? i_icache_address : icache_read_addr_r;
|
assign icache_read_addr_c = i_icache_req ? i_icache_address : icache_read_addr_r;
|
|
|
assign dcache_req_c = dcache_cached_rreq_c || dcache_cached_wreq_c || dcache_uncached_rreq_c || dcache_uncached_wreq_c;
|
assign dcache_req_c = dcache_cached_rreq_c || dcache_cached_wreq_c || dcache_uncached_rreq_c || dcache_uncached_wreq_c;
|
assign write_req_c = dcache_cached_wreq_c || dcache_uncached_wreq_c;
|
assign write_req_c = dcache_cached_wreq_c || dcache_uncached_wreq_c;
|
|
|
assign start_access = !wait_write_ack && (dcache_req_c || icache_read_req_c);
|
assign start_access = !wait_write_ack && (dcache_req_c || icache_read_req_c);
|
|
|
// For writes the byte enable is always 4'hf
|
// For writes the byte enable is always 4'hf
|
assign byte_enable = write_req_c ? i_dcache_byte_enable : 4'hf;
|
assign byte_enable = write_req_c ? i_dcache_byte_enable : 4'hf;
|
|
|
|
|
assign dcache_cached_wready = (dcache_cached_wreq_c && wishbone_st == WB_IDLE);
|
assign dcache_cached_wready = (dcache_cached_wreq_c && wishbone_st == WB_IDLE);
|
assign dcache_uncached_wready = (dcache_uncached_wreq_c && wishbone_st == WB_IDLE);
|
assign dcache_uncached_wready = (dcache_uncached_wreq_c && wishbone_st == WB_IDLE);
|
assign dcache_cached_wreq_c = dcache_cached_wreq_in || dcache_cached_wreq_r;
|
assign dcache_cached_wreq_c = dcache_cached_wreq_in || dcache_cached_wreq_r;
|
assign dcache_uncached_wreq_c = dcache_uncached_wreq_in || dcache_uncached_wreq_r;
|
assign dcache_uncached_wreq_c = dcache_uncached_wreq_in || dcache_uncached_wreq_r;
|
|
|
|
|
// ======================================
|
// ======================================
|
// Register Accesses
|
// Register Accesses
|
// ======================================
|
// ======================================
|
|
|
assign extra_write = wishbone_st == WB_IDLE && !i_wb_ack && ((dcache_cached_wreq_c && dcache_cached_wready)||
|
assign extra_write = wishbone_st == WB_IDLE && !i_wb_ack && ((dcache_cached_wreq_c && dcache_cached_wready)||
|
(dcache_uncached_wreq_c && dcache_uncached_wready));
|
(dcache_uncached_wreq_c && dcache_uncached_wready));
|
|
|
always @( posedge i_clk )
|
always @( posedge i_clk )
|
if ( wishbone_st == WB_WAIT_ACK && i_wb_ack && extra_write_r )
|
if ( wishbone_st == WB_WAIT_ACK && i_wb_ack && extra_write_r )
|
o_wb_dat <= extra_write_data_r;
|
o_wb_dat <= extra_write_data_r;
|
else if ( start_access )
|
else if ( start_access )
|
o_wb_dat <= i_dcache_write_data;
|
o_wb_dat <= i_dcache_write_data;
|
|
|
|
|
|
|
always @( posedge i_clk )
|
always @( posedge i_clk )
|
begin
|
begin
|
icache_read_req_r <= icache_read_req_in || icache_read_req_c;
|
icache_read_req_r <= icache_read_req_in || icache_read_req_c;
|
icache_read_qword_r <= i_icache_qword || icache_read_qword_c;
|
icache_read_qword_r <= i_icache_qword || icache_read_qword_c;
|
if ( i_icache_req ) icache_read_addr_r <= i_icache_address;
|
if ( i_icache_req ) icache_read_addr_r <= i_icache_address;
|
|
|
dcache_read_qword_r <= i_dcache_qword || dcache_read_qword_c;
|
dcache_read_qword_r <= i_dcache_qword || dcache_read_qword_c;
|
dcache_cached_wreq_r <= dcache_cached_wreq_c && (wishbone_st != WB_IDLE || (o_wb_stb && !i_wb_ack));
|
dcache_cached_wreq_r <= dcache_cached_wreq_c && (wishbone_st != WB_IDLE || (o_wb_stb && !i_wb_ack));
|
dcache_uncached_wreq_r <= dcache_uncached_wreq_c && (wishbone_st != WB_IDLE || (o_wb_stb && !i_wb_ack));
|
dcache_uncached_wreq_r <= dcache_uncached_wreq_c && (wishbone_st != WB_IDLE || (o_wb_stb && !i_wb_ack));
|
|
|
|
|
// A buffer to hold a second write while on eis in progress
|
// A buffer to hold a second write while on eis in progress
|
if ( extra_write )
|
if ( extra_write )
|
begin
|
begin
|
extra_write_data_r <= i_dcache_write_data;
|
extra_write_data_r <= i_dcache_write_data;
|
extra_write_address_r <= i_dcache_address;
|
extra_write_address_r <= i_dcache_address;
|
extra_write_be_r <= i_dcache_byte_enable;
|
extra_write_be_r <= i_dcache_byte_enable;
|
end
|
end
|
|
|
|
|
// The flag can be set during any state but only cleared during WB_IDLE or WB_WAIT_ACK
|
// The flag can be set during any state but only cleared during WB_IDLE or WB_WAIT_ACK
|
if ( dcache_cached_rreq_r )
|
if ( dcache_cached_rreq_r )
|
begin
|
begin
|
if ( wishbone_st == WB_IDLE || wishbone_st == WB_WAIT_ACK )
|
if ( wishbone_st == WB_IDLE || wishbone_st == WB_WAIT_ACK )
|
dcache_cached_rreq_r <= dcache_cached_rreq_c && !o_dcache_cached_ready;
|
dcache_cached_rreq_r <= dcache_cached_rreq_c && !o_dcache_cached_ready;
|
end
|
end
|
else
|
else
|
dcache_cached_rreq_r <= dcache_cached_rreq_c && !o_dcache_cached_ready;
|
dcache_cached_rreq_r <= dcache_cached_rreq_c && !o_dcache_cached_ready;
|
if ( dcache_uncached_rreq_r )
|
if ( dcache_uncached_rreq_r )
|
begin
|
begin
|
if ( wishbone_st == WB_IDLE || wishbone_st == WB_WAIT_ACK )
|
if ( wishbone_st == WB_IDLE || wishbone_st == WB_WAIT_ACK )
|
dcache_uncached_rreq_r <= dcache_uncached_rreq_c && !o_dcache_uncached_ready;
|
dcache_uncached_rreq_r <= dcache_uncached_rreq_c && !o_dcache_uncached_ready;
|
end
|
end
|
else
|
else
|
dcache_uncached_rreq_r <= dcache_uncached_rreq_c && !o_dcache_uncached_ready;
|
dcache_uncached_rreq_r <= dcache_uncached_rreq_c && !o_dcache_uncached_ready;
|
end
|
end
|
|
|
assign wait_write_ack = o_wb_stb && o_wb_we && !i_wb_ack;
|
assign wait_write_ack = o_wb_stb && o_wb_we && !i_wb_ack;
|
|
|
|
|
always @( posedge i_clk )
|
always @( posedge i_clk )
|
case ( wishbone_st )
|
case ( wishbone_st )
|
WB_IDLE :
|
WB_IDLE :
|
begin
|
begin
|
extra_write_r <= extra_write;
|
extra_write_r <= extra_write;
|
|
|
if ( start_access )
|
if ( start_access )
|
begin
|
begin
|
o_wb_stb <= 1'd1;
|
o_wb_stb <= 1'd1;
|
o_wb_cyc <= 1'd1;
|
o_wb_cyc <= 1'd1;
|
o_wb_sel <= byte_enable;
|
o_wb_sel <= byte_enable;
|
end
|
end
|
else if ( !wait_write_ack )
|
else if ( !wait_write_ack )
|
begin
|
begin
|
o_wb_stb <= 1'd0;
|
o_wb_stb <= 1'd0;
|
|
|
// Hold cyc high after an exclusive access
|
// Hold cyc high after an exclusive access
|
// to hold ownership of the wishbone bus
|
// to hold ownership of the wishbone bus
|
o_wb_cyc <= exclusive_access;
|
o_wb_cyc <= exclusive_access;
|
end
|
end
|
|
|
if ( wait_write_ack )
|
if ( wait_write_ack )
|
begin
|
begin
|
// still waiting for last (write) access to complete
|
// still waiting for last (write) access to complete
|
wishbone_st <= WB_WAIT_ACK;
|
wishbone_st <= WB_WAIT_ACK;
|
servicing_dcache_cached_read_r <= dcache_cached_rreq_c;
|
servicing_dcache_cached_read_r <= dcache_cached_rreq_c;
|
servicing_dcache_uncached_read_r <= dcache_uncached_rreq_c;
|
servicing_dcache_uncached_read_r <= dcache_uncached_rreq_c;
|
end
|
end
|
// dcache accesses have priority over icache
|
// dcache accesses have priority over icache
|
else if ( dcache_cached_rreq_c || dcache_uncached_rreq_c )
|
else if ( dcache_cached_rreq_c || dcache_uncached_rreq_c )
|
begin
|
begin
|
if ( dcache_cached_rreq_c )
|
if ( dcache_cached_rreq_c )
|
servicing_dcache_cached_read_r <= 1'd1;
|
servicing_dcache_cached_read_r <= 1'd1;
|
else if ( dcache_uncached_rreq_c )
|
else if ( dcache_uncached_rreq_c )
|
servicing_dcache_uncached_read_r <= 1'd1;
|
servicing_dcache_uncached_read_r <= 1'd1;
|
|
|
if ( dcache_read_qword_c )
|
if ( dcache_read_qword_c )
|
wishbone_st <= WB_BURST1;
|
wishbone_st <= WB_BURST1;
|
else
|
else
|
wishbone_st <= WB_WAIT_ACK;
|
wishbone_st <= WB_WAIT_ACK;
|
exclusive_access <= i_exclusive;
|
exclusive_access <= i_exclusive;
|
end
|
end
|
// The core does not currently issue exclusive write requests
|
// The core does not currently issue exclusive write requests
|
// but there's no reason why this might not be added some
|
// but there's no reason why this might not be added some
|
// time in the future so allow for it here
|
// time in the future so allow for it here
|
else if ( write_req_c )
|
else if ( write_req_c )
|
begin
|
begin
|
exclusive_access <= i_exclusive;
|
exclusive_access <= i_exclusive;
|
end
|
end
|
// do a burst of 4 read to fill a cache line
|
// do a burst of 4 read to fill a cache line
|
else if ( icache_read_req_c && icache_read_qword_c )
|
else if ( icache_read_req_c && icache_read_qword_c )
|
begin
|
begin
|
wishbone_st <= WB_BURST1;
|
wishbone_st <= WB_BURST1;
|
exclusive_access <= 1'd0;
|
exclusive_access <= 1'd0;
|
servicing_icache_r <= 1'd1;
|
servicing_icache_r <= 1'd1;
|
end
|
end
|
// single word read request from fetch stage
|
// single word read request from fetch stage
|
else if ( icache_read_req_c )
|
else if ( icache_read_req_c )
|
begin
|
begin
|
wishbone_st <= WB_WAIT_ACK;
|
wishbone_st <= WB_WAIT_ACK;
|
exclusive_access <= 1'd0;
|
exclusive_access <= 1'd0;
|
servicing_icache_r <= 1'd1;
|
servicing_icache_r <= 1'd1;
|
end
|
end
|
|
|
|
|
if ( start_access )
|
if ( start_access )
|
begin
|
begin
|
if ( dcache_req_c )
|
if ( dcache_req_c )
|
begin
|
begin
|
o_wb_we <= write_req_c;
|
o_wb_we <= write_req_c;
|
// only update these on new wb access to make debug easier
|
// only update these on new wb access to make debug easier
|
o_wb_adr[31:2] <= i_dcache_address[31:2];
|
o_wb_adr[31:2] <= i_dcache_address[31:2];
|
o_wb_adr[1:0] <= byte_enable == 4'b0001 ? 2'd0 :
|
o_wb_adr[1:0] <= byte_enable == 4'b0001 ? 2'd0 :
|
byte_enable == 4'b0010 ? 2'd1 :
|
byte_enable == 4'b0010 ? 2'd1 :
|
byte_enable == 4'b0100 ? 2'd2 :
|
byte_enable == 4'b0100 ? 2'd2 :
|
byte_enable == 4'b1000 ? 2'd3 :
|
byte_enable == 4'b1000 ? 2'd3 :
|
|
|
byte_enable == 4'b0011 ? 2'd0 :
|
byte_enable == 4'b0011 ? 2'd0 :
|
byte_enable == 4'b1100 ? 2'd2 :
|
byte_enable == 4'b1100 ? 2'd2 :
|
|
|
2'd0 ;
|
2'd0 ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
o_wb_we <= 1'd0;
|
o_wb_we <= 1'd0;
|
o_wb_adr[31:0] <= {icache_read_addr_c[31:2], 2'd0};
|
o_wb_adr[31:0] <= {icache_read_addr_c[31:2], 2'd0};
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
|
|
// Read burst, wait for first ack
|
// Read burst, wait for first ack
|
WB_BURST1:
|
WB_BURST1:
|
if ( i_wb_ack )
|
if ( i_wb_ack )
|
begin
|
begin
|
// burst of 4 that wraps
|
// burst of 4 that wraps
|
o_wb_adr[3:2] <= o_wb_adr[3:2] + 1'd1;
|
o_wb_adr[3:2] <= o_wb_adr[3:2] + 1'd1;
|
wishbone_st <= WB_BURST2;
|
wishbone_st <= WB_BURST2;
|
end
|
end
|
|
|
|
|
// Read burst, wait for second ack
|
// Read burst, wait for second ack
|
WB_BURST2:
|
WB_BURST2:
|
if ( i_wb_ack )
|
if ( i_wb_ack )
|
begin
|
begin
|
// burst of 4 that wraps
|
// burst of 4 that wraps
|
o_wb_adr[3:2] <= o_wb_adr[3:2] + 1'd1;
|
o_wb_adr[3:2] <= o_wb_adr[3:2] + 1'd1;
|
wishbone_st <= WB_BURST3;
|
wishbone_st <= WB_BURST3;
|
end
|
end
|
|
|
|
|
// Read burst, wait for third ack
|
// Read burst, wait for third ack
|
WB_BURST3:
|
WB_BURST3:
|
if ( i_wb_ack )
|
if ( i_wb_ack )
|
begin
|
begin
|
// burst of 4 that wraps
|
// burst of 4 that wraps
|
o_wb_adr[3:2] <= o_wb_adr[3:2] + 1'd1;
|
o_wb_adr[3:2] <= o_wb_adr[3:2] + 1'd1;
|
wishbone_st <= WB_WAIT_ACK;
|
wishbone_st <= WB_WAIT_ACK;
|
end
|
end
|
|
|
|
|
// Wait for the wishbone ack to be asserted
|
// Wait for the wishbone ack to be asserted
|
WB_WAIT_ACK:
|
WB_WAIT_ACK:
|
if ( i_wb_ack )
|
if ( i_wb_ack )
|
// Another write that was acked and needs to be sent before returning to IDLE ?
|
// Another write that was acked and needs to be sent before returning to IDLE ?
|
if ( extra_write_r )
|
if ( extra_write_r )
|
begin
|
begin
|
extra_write_r <= 'd0;
|
extra_write_r <= 'd0;
|
o_wb_stb <= 1'd1;
|
o_wb_stb <= 1'd1;
|
o_wb_cyc <= exclusive_access;
|
o_wb_cyc <= exclusive_access;
|
o_wb_sel <= extra_write_be_r;
|
o_wb_sel <= extra_write_be_r;
|
o_wb_we <= 1'd1;
|
o_wb_we <= 1'd1;
|
o_wb_adr[31:0] <= extra_write_address_r;
|
o_wb_adr[31:0] <= extra_write_address_r;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
wishbone_st <= WB_IDLE;
|
wishbone_st <= WB_IDLE;
|
o_wb_stb <= 1'd0;
|
o_wb_stb <= 1'd0;
|
o_wb_cyc <= exclusive_access;
|
o_wb_cyc <= exclusive_access;
|
o_wb_we <= 1'd0;
|
o_wb_we <= 1'd0;
|
servicing_dcache_cached_read_r <= 1'd0;
|
servicing_dcache_cached_read_r <= 1'd0;
|
servicing_dcache_uncached_read_r <= 1'd0;
|
servicing_dcache_uncached_read_r <= 1'd0;
|
servicing_icache_r <= 1'd0;
|
servicing_icache_r <= 1'd0;
|
end
|
end
|
|
|
|
|
endcase
|
endcase
|
|
|
// ========================================================
|
// ========================================================
|
// Debug Wishbone bus - not synthesizable
|
// Debug Wishbone bus - not synthesizable
|
// ========================================================
|
// ========================================================
|
//synopsys translate_off
|
//synopsys translate_off
|
wire [(14*8)-1:0] xWB_STATE;
|
wire [(14*8)-1:0] xWB_STATE;
|
|
|
|
|
assign xWB_STATE = wishbone_st == WB_IDLE ? "WB_IDLE" :
|
assign xWB_STATE = wishbone_st == WB_IDLE ? "WB_IDLE" :
|
wishbone_st == WB_BURST1 ? "WB_BURST1" :
|
wishbone_st == WB_BURST1 ? "WB_BURST1" :
|
wishbone_st == WB_BURST2 ? "WB_BURST2" :
|
wishbone_st == WB_BURST2 ? "WB_BURST2" :
|
wishbone_st == WB_BURST3 ? "WB_BURST3" :
|
wishbone_st == WB_BURST3 ? "WB_BURST3" :
|
wishbone_st == WB_WAIT_ACK ? "WB_WAIT_ACK" :
|
wishbone_st == WB_WAIT_ACK ? "WB_WAIT_ACK" :
|
"UNKNOWN" ;
|
"UNKNOWN" ;
|
|
|
//synopsys translate_on
|
//synopsys translate_on
|
|
|
endmodule
|
endmodule
|
|
|
|
|