| Line 139... |
Line 139... |
reg dcache_read_qword_r = 'd0;
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reg dcache_read_qword_r = 'd0;
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wire icache_read_req_in;
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wire icache_read_req_in;
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wire icache_read_ready;
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wire icache_read_ready;
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reg servicing_dcache_cached_read_r = 'd0;
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reg servicing_dcache_cached_read_r = 'd0;
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reg servicing_dcache_uncached_read_r = 'd0;
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reg servicing_dcache_uncached_read_r = 'd0;
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reg servicing_dcache_cached_write_r = 'd0;
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reg servicing_dcache_uncached_write_r = 'd0;
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reg servicing_icache_r = 'd0;
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reg servicing_icache_r = 'd0;
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wire extra_write;
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wire buffer_write;
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reg extra_write_r = 'd0;
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reg buffer_write_r = 'd0;
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reg [31:0] extra_write_data_r;
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reg [31:0] buffer_write_data_r;
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reg [31:0] extra_write_address_r;
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reg [31:0] buffer_write_address_r;
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reg [3:0] extra_write_be_r;
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reg [3:0] buffer_write_be_r;
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wire write_ack;
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assign read_ack = !o_wb_we && i_wb_ack;
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assign read_ack = !o_wb_we && i_wb_ack;
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assign dcache_cached_rready = dcache_cached_rreq_r && servicing_dcache_cached_read_r && read_ack;
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assign dcache_cached_rready = dcache_cached_rreq_r && servicing_dcache_cached_read_r && read_ack;
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assign dcache_uncached_rready = dcache_uncached_rreq_r && servicing_dcache_uncached_read_r && read_ack;
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assign dcache_uncached_rready = dcache_uncached_rreq_r && servicing_dcache_uncached_read_r && read_ack;
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assign dcache_cached_wready = (dcache_cached_wreq_c && wishbone_st == WB_IDLE && !dcache_cached_rreq_c) ||
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(servicing_dcache_cached_write_r && i_wb_ack && wishbone_st == WB_WAIT_ACK && !dcache_cached_rreq_c);
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assign dcache_uncached_wready = (dcache_uncached_wreq_c && wishbone_st == WB_IDLE && !dcache_uncached_rreq_c) ||
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(servicing_dcache_uncached_write_r && i_wb_ack && wishbone_st == WB_WAIT_ACK && !dcache_uncached_rreq_c);
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assign o_dcache_cached_ready = dcache_cached_rready || dcache_cached_wready;
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assign o_dcache_cached_ready = dcache_cached_rready || dcache_cached_wready;
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assign o_dcache_uncached_ready = dcache_uncached_rready || dcache_uncached_wready;
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assign o_dcache_uncached_ready = dcache_uncached_rready || dcache_uncached_wready;
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assign o_dcache_read_data = i_wb_dat;
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assign o_dcache_read_data = i_wb_dat;
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assign icache_read_ready = servicing_icache_r && read_ack;
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assign icache_read_ready = servicing_icache_r && read_ack;
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assign o_icache_ready = icache_read_ready;
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assign o_icache_ready = icache_read_ready;
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assign o_icache_read_data = i_wb_dat;
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assign o_icache_read_data = i_wb_dat;
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assign dcache_cached_rreq_in = i_dcache_cached_req && !i_dcache_write;
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assign dcache_cached_rreq_in = i_dcache_cached_req && !i_dcache_write;
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assign dcache_cached_wreq_in = i_dcache_cached_req && i_dcache_write;
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assign dcache_cached_wreq_in = i_dcache_cached_req && i_dcache_write;
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assign dcache_uncached_rreq_in = i_dcache_uncached_req && !i_dcache_write;
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assign dcache_uncached_rreq_in = i_dcache_uncached_req && !i_dcache_write;
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assign dcache_uncached_wreq_in = i_dcache_uncached_req && i_dcache_write;
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assign dcache_uncached_wreq_in = i_dcache_uncached_req && i_dcache_write;
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assign icache_read_req_in = i_icache_req && !o_icache_ready;
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assign icache_read_req_in = i_icache_req && !o_icache_ready;
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| Line 184... |
Line 191... |
assign start_access = !wait_write_ack && (dcache_req_c || icache_read_req_c);
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assign start_access = !wait_write_ack && (dcache_req_c || icache_read_req_c);
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// For writes the byte enable is always 4'hf
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// For writes the byte enable is always 4'hf
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assign byte_enable = write_req_c ? i_dcache_byte_enable : 4'hf;
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assign byte_enable = write_req_c ? i_dcache_byte_enable : 4'hf;
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assign dcache_cached_wready = (dcache_cached_wreq_c && wishbone_st == WB_IDLE);
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assign dcache_uncached_wready = (dcache_uncached_wreq_c && wishbone_st == WB_IDLE);
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assign dcache_cached_wreq_c = dcache_cached_wreq_in || dcache_cached_wreq_r;
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assign dcache_cached_wreq_c = dcache_cached_wreq_in || dcache_cached_wreq_r;
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assign dcache_uncached_wreq_c = dcache_uncached_wreq_in || dcache_uncached_wreq_r;
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assign dcache_uncached_wreq_c = dcache_uncached_wreq_in || dcache_uncached_wreq_r;
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// ======================================
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// ======================================
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// Register Accesses
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// Register Accesses
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// ======================================
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// ======================================
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assign extra_write = wishbone_st == WB_IDLE && !i_wb_ack && ((dcache_cached_wreq_c && dcache_cached_wready)||
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assign buffer_write = dcache_cached_wreq_in || dcache_uncached_wreq_in;
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(dcache_uncached_wreq_c && dcache_uncached_wready));
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assign write_buffered = dcache_uncached_wreq_r || dcache_uncached_wreq_r;
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always @( posedge i_clk )
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if ( wishbone_st == WB_WAIT_ACK && i_wb_ack && extra_write_r )
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o_wb_dat <= extra_write_data_r;
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else if ( start_access )
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o_wb_dat <= i_dcache_write_data;
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always @( posedge i_clk )
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always @( posedge i_clk )
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begin
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begin
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icache_read_req_r <= icache_read_req_in || icache_read_req_c;
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icache_read_req_r <= icache_read_req_in || icache_read_req_c;
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icache_read_qword_r <= i_icache_qword || icache_read_qword_c;
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icache_read_qword_r <= i_icache_qword || icache_read_qword_c;
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if ( i_icache_req ) icache_read_addr_r <= i_icache_address;
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if ( i_icache_req ) icache_read_addr_r <= i_icache_address;
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dcache_read_qword_r <= i_dcache_qword || dcache_read_qword_c;
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dcache_read_qword_r <= i_dcache_qword || dcache_read_qword_c;
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dcache_cached_wreq_r <= dcache_cached_wreq_c && (wishbone_st != WB_IDLE || (o_wb_stb && !i_wb_ack));
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dcache_uncached_wreq_r <= dcache_uncached_wreq_c && (wishbone_st != WB_IDLE || (o_wb_stb && !i_wb_ack));
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// Buffer Write requests
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case (wishbone_st)
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WB_WAIT_ACK :
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begin
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if (servicing_dcache_uncached_write_r && i_wb_ack && !buffer_write)
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dcache_uncached_wreq_r <= 1'd0;
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else
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dcache_uncached_wreq_r <= dcache_uncached_wreq_c;
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if (servicing_dcache_cached_write_r && i_wb_ack && !buffer_write)
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dcache_cached_wreq_r <= 1'd0;
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else
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dcache_cached_wreq_r <= dcache_cached_wreq_c;
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end
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WB_IDLE:
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begin
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if (dcache_uncached_wreq_c && o_wb_stb && !i_wb_ack)
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dcache_uncached_wreq_r <= 1'd1;
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else
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dcache_uncached_wreq_r <= 1'd0;
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// A buffer to hold a second write while on eis in progress
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if (dcache_cached_wreq_c && o_wb_stb && !i_wb_ack)
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if ( extra_write )
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dcache_cached_wreq_r <= 1'd1;
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else
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dcache_cached_wreq_r <= 1'd0;
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end
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default:
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begin
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begin
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extra_write_data_r <= i_dcache_write_data;
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dcache_uncached_wreq_r <= dcache_uncached_wreq_c;
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extra_write_address_r <= i_dcache_address;
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dcache_cached_wreq_r <= dcache_cached_wreq_c;
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extra_write_be_r <= i_dcache_byte_enable;
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end
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endcase
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// A buffer to hold a second write while on is in progress
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if ( buffer_write )
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begin
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buffer_write_data_r <= i_dcache_write_data;
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buffer_write_address_r <= i_dcache_address;
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buffer_write_be_r <= i_dcache_byte_enable;
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end
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end
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// The flag can be set during any state but only cleared during WB_IDLE or WB_WAIT_ACK
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// The flag can be set during any state but only cleared during WB_IDLE or WB_WAIT_ACK
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if ( dcache_cached_rreq_r )
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if ( dcache_cached_rreq_r )
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begin
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begin
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if ( wishbone_st == WB_IDLE || wishbone_st == WB_WAIT_ACK )
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if ( wishbone_st == WB_IDLE || wishbone_st == WB_WAIT_ACK )
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dcache_cached_rreq_r <= dcache_cached_rreq_c && !o_dcache_cached_ready;
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dcache_cached_rreq_r <= dcache_cached_rreq_c && !o_dcache_cached_ready;
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end
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end
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else
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else
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dcache_cached_rreq_r <= dcache_cached_rreq_c && !o_dcache_cached_ready;
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dcache_cached_rreq_r <= dcache_cached_rreq_c && (!o_dcache_cached_ready || dcache_cached_wreq_r);
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if ( dcache_uncached_rreq_r )
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if ( dcache_uncached_rreq_r )
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begin
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begin
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if ( wishbone_st == WB_IDLE || wishbone_st == WB_WAIT_ACK )
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if ( wishbone_st == WB_IDLE || wishbone_st == WB_WAIT_ACK )
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dcache_uncached_rreq_r <= dcache_uncached_rreq_c && !o_dcache_uncached_ready;
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dcache_uncached_rreq_r <= dcache_uncached_rreq_c && !o_dcache_uncached_ready;
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end
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end
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else
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else
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dcache_uncached_rreq_r <= dcache_uncached_rreq_c && !o_dcache_uncached_ready;
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dcache_uncached_rreq_r <= dcache_uncached_rreq_c && (!o_dcache_uncached_ready || dcache_uncached_wreq_r);
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end
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end
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assign wait_write_ack = o_wb_stb && o_wb_we && !i_wb_ack;
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assign wait_write_ack = o_wb_stb && o_wb_we && !i_wb_ack;
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assign write_ack = o_wb_stb && o_wb_we && i_wb_ack;
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always @( posedge i_clk )
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always @( posedge i_clk )
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case ( wishbone_st )
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case ( wishbone_st )
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WB_IDLE :
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WB_IDLE :
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begin
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begin
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extra_write_r <= extra_write;
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if ( start_access )
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if ( start_access )
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begin
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begin
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o_wb_stb <= 1'd1;
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o_wb_stb <= 1'd1;
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o_wb_cyc <= 1'd1;
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o_wb_cyc <= 1'd1;
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o_wb_sel <= byte_enable;
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o_wb_sel <= byte_enable;
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o_wb_dat <= write_buffered ? buffer_write_data_r : i_dcache_write_data;
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end
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end
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else if ( !wait_write_ack )
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else if ( !wait_write_ack )
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begin
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begin
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o_wb_stb <= 1'd0;
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o_wb_stb <= 1'd0;
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| Line 273... |
Line 305... |
begin
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begin
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// still waiting for last (write) access to complete
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// still waiting for last (write) access to complete
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wishbone_st <= WB_WAIT_ACK;
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wishbone_st <= WB_WAIT_ACK;
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servicing_dcache_cached_read_r <= dcache_cached_rreq_c;
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servicing_dcache_cached_read_r <= dcache_cached_rreq_c;
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servicing_dcache_uncached_read_r <= dcache_uncached_rreq_c;
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servicing_dcache_uncached_read_r <= dcache_uncached_rreq_c;
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servicing_dcache_cached_write_r <= dcache_cached_wreq_c;
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servicing_dcache_uncached_write_r <= dcache_uncached_wreq_c;
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end
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end
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// dcache accesses have priority over icache
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// dcache accesses have priority over icache
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else if ( dcache_cached_rreq_c || dcache_uncached_rreq_c )
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else if ( dcache_cached_rreq_c || dcache_uncached_rreq_c )
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begin
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begin
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if ( dcache_cached_rreq_c )
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if ( dcache_cached_rreq_c )
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| Line 370... |
Line 404... |
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// Wait for the wishbone ack to be asserted
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// Wait for the wishbone ack to be asserted
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WB_WAIT_ACK:
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WB_WAIT_ACK:
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if ( i_wb_ack )
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if ( i_wb_ack )
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begin
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servicing_dcache_cached_read_r <= 1'd0;
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servicing_dcache_uncached_read_r <= 1'd0;
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servicing_dcache_cached_write_r <= 1'd0;
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servicing_dcache_uncached_write_r <= 1'd0;
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servicing_icache_r <= 1'd0;
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// Another write that was acked and needs to be sent before returning to IDLE ?
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// Another write that was acked and needs to be sent before returning to IDLE ?
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if ( extra_write_r )
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if ( write_buffered )
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begin
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begin
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extra_write_r <= 'd0;
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wishbone_st <= WB_IDLE;
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o_wb_stb <= 1'd1;
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o_wb_stb <= 1'd1;
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o_wb_cyc <= exclusive_access;
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o_wb_cyc <= exclusive_access;
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o_wb_sel <= extra_write_be_r;
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o_wb_sel <= buffer_write_be_r;
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o_wb_we <= 1'd1;
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o_wb_we <= 1'd1;
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o_wb_adr[31:0] <= extra_write_address_r;
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o_wb_adr[31:0] <= buffer_write_address_r;
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o_wb_dat <= buffer_write_data_r;
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end
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end
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else
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else
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begin
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begin
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wishbone_st <= WB_IDLE;
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wishbone_st <= WB_IDLE;
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o_wb_stb <= 1'd0;
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o_wb_stb <= 1'd0;
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o_wb_cyc <= exclusive_access;
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o_wb_cyc <= exclusive_access;
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o_wb_we <= 1'd0;
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o_wb_we <= 1'd0;
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servicing_dcache_cached_read_r <= 1'd0;
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servicing_dcache_uncached_read_r <= 1'd0;
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servicing_icache_r <= 1'd0;
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end
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end
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end
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endcase
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endcase
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// ========================================================
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// ========================================================
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// Debug Wishbone bus - not synthesizable
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// Debug Wishbone bus - not synthesizable
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