//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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// //
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// //
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// Interrupt Controller for Amber //
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// Interrupt Controller for Amber //
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// //
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// //
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// This file is part of the Amber project //
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// This file is part of the Amber project //
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// http://www.opencores.org/project,amber //
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// http://www.opencores.org/project,amber //
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// //
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// //
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// Description //
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// Description //
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// Wishbone slave module that arbitrates between a number of //
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// Wishbone slave module that arbitrates between a number of //
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// interrupt sources.
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// interrupt sources.
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// //
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// //
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// Author(s): //
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// Author(s): //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// //
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// //
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//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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// //
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// //
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// Copyright (C) 2010 Authors and OPENCORES.ORG //
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// Copyright (C) 2010 Authors and OPENCORES.ORG //
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// //
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// //
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// This source file may be used and distributed without //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// the original copyright notice and the associated disclaimer. //
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// //
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// //
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// This source file is free software; you can redistribute it //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// later version. //
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// //
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// //
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// This source is distributed in the hope that it will be //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// details. //
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// //
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// //
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// You should have received a copy of the GNU Lesser General //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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// //
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//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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module interrupt_controller (
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module interrupt_controller #(
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parameter WB_DWIDTH = 32,
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parameter WB_SWIDTH = 4
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)(
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input i_clk,
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input i_clk,
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input [31:0] i_wb_adr,
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input [31:0] i_wb_adr,
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input [3:0] i_wb_sel,
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input [WB_SWIDTH-1:0] i_wb_sel,
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input i_wb_we,
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input i_wb_we,
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output [31:0] o_wb_dat,
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output [WB_DWIDTH-1:0] o_wb_dat,
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input [31:0] i_wb_dat,
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input [WB_DWIDTH-1:0] i_wb_dat,
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input i_wb_cyc,
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input i_wb_cyc,
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input i_wb_stb,
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input i_wb_stb,
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output o_wb_ack,
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output o_wb_ack,
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output o_wb_err,
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output o_wb_err,
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output o_irq,
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output o_irq,
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output o_firq,
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output o_firq,
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input i_uart0_int,
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input i_uart0_int,
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input i_uart1_int,
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input i_uart1_int,
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input i_ethmac_int,
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input i_ethmac_int,
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input i_test_reg_irq,
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input i_test_reg_irq,
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input i_test_reg_firq,
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input i_test_reg_firq,
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input [2:0] i_tm_timer_int
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input [2:0] i_tm_timer_int
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);
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);
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`include "register_addresses.v"
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`include "register_addresses.v"
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// Wishbone registers
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// Wishbone registers
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reg [31:0] irq0_enable_reg = 'd0;
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reg [31:0] irq0_enable_reg = 'd0;
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reg [31:0] firq0_enable_reg = 'd0;
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reg [31:0] firq0_enable_reg = 'd0;
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reg [31:0] irq1_enable_reg = 'd0;
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reg [31:0] irq1_enable_reg = 'd0;
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reg [31:0] firq1_enable_reg = 'd0;
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reg [31:0] firq1_enable_reg = 'd0;
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reg softint_0_reg = 'd0;
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reg softint_0_reg = 'd0;
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reg softint_1_reg = 'd0;
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reg softint_1_reg = 'd0;
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wire [31:0] raw_interrupts;
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wire [31:0] raw_interrupts;
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wire [31:0] irq0_interrupts;
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wire [31:0] irq0_interrupts;
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wire [31:0] firq0_interrupts;
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wire [31:0] firq0_interrupts;
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wire [31:0] irq1_interrupts;
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wire [31:0] irq1_interrupts;
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wire [31:0] firq1_interrupts;
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wire [31:0] firq1_interrupts;
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wire irq_0;
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wire irq_0;
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wire firq_0;
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wire firq_0;
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wire irq_1;
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wire irq_1;
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wire firq_1;
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wire firq_1;
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// Wishbone interface
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// Wishbone interface
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reg [31:0] wb_rdata = 'd0;
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reg [31:0] wb_rdata32 = 'd0;
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wire wb_start_write;
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wire wb_start_write;
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wire wb_start_read;
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wire wb_start_read;
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reg wb_start_read_d1 = 'd0;
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reg wb_start_read_d1 = 'd0;
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wire [31:0] wb_wdata32;
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// ======================================================
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// ======================================================
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// Wishbone Interface
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// Wishbone Interface
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// ======================================================
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// ======================================================
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// Can't start a write while a read is completing. The ack for the read cycle
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// Can't start a write while a read is completing. The ack for the read cycle
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// needs to be sent first
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// needs to be sent first
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assign wb_start_write = i_wb_stb && i_wb_we && !wb_start_read_d1;
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assign wb_start_write = i_wb_stb && i_wb_we && !wb_start_read_d1;
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assign wb_start_read = i_wb_stb && !i_wb_we && !o_wb_ack;
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assign wb_start_read = i_wb_stb && !i_wb_we && !o_wb_ack;
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always @( posedge i_clk )
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always @( posedge i_clk )
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wb_start_read_d1 <= wb_start_read;
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wb_start_read_d1 <= wb_start_read;
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assign o_wb_dat = wb_rdata;
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assign o_wb_err = 1'd0;
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assign o_wb_err = 1'd0;
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assign o_wb_ack = i_wb_stb && ( wb_start_write || wb_start_read_d1 );
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assign o_wb_ack = i_wb_stb && ( wb_start_write || wb_start_read_d1 );
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generate
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if (WB_DWIDTH == 128)
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begin : wb128
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assign wb_wdata32 = i_wb_adr[3:2] == 2'd3 ? i_wb_dat[127:96] :
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i_wb_adr[3:2] == 2'd2 ? i_wb_dat[ 95:64] :
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i_wb_adr[3:2] == 2'd1 ? i_wb_dat[ 63:32] :
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i_wb_dat[ 31: 0] ;
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assign o_wb_dat = {4{wb_rdata32}};
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end
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else
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begin : wb32
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assign wb_wdata32 = i_wb_dat;
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assign o_wb_dat = wb_rdata32;
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end
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endgenerate
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// ======================================
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// ======================================
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// Interrupts
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// Interrupts
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// ======================================
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// ======================================
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assign raw_interrupts = {23'd0,
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assign raw_interrupts = {23'd0,
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i_ethmac_int, // 8: Ethernet MAC interrupt
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i_ethmac_int, // 8: Ethernet MAC interrupt
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i_tm_timer_int[2], // 7: Timer Module Interrupt 2
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i_tm_timer_int[2], // 7: Timer Module Interrupt 2
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i_tm_timer_int[1], // 6: Timer Module Interrupt 1
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i_tm_timer_int[1], // 6: Timer Module Interrupt 1
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i_tm_timer_int[0], // 5: Timer Module Interrupt 0
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i_tm_timer_int[0], // 5: Timer Module Interrupt 0
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1'd0,
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1'd0,
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1'd0,
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1'd0,
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i_uart1_int, // 2: Uart 1 interrupt
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i_uart1_int, // 2: Uart 1 interrupt
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i_uart0_int, // 1: Uart 0 interrupt
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i_uart0_int, // 1: Uart 0 interrupt
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1'd0 // 0: Software interrupt not
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1'd0 // 0: Software interrupt not
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}; // here because its not maskable
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}; // here because its not maskable
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assign irq0_interrupts = {raw_interrupts[31:1], softint_0_reg} & irq0_enable_reg;
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assign irq0_interrupts = {raw_interrupts[31:1], softint_0_reg} & irq0_enable_reg;
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assign firq0_interrupts = raw_interrupts & firq0_enable_reg;
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assign firq0_interrupts = raw_interrupts & firq0_enable_reg;
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assign irq1_interrupts = {raw_interrupts[31:1], softint_1_reg} & irq1_enable_reg;
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assign irq1_interrupts = {raw_interrupts[31:1], softint_1_reg} & irq1_enable_reg;
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assign firq1_interrupts = raw_interrupts & firq1_enable_reg;
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assign firq1_interrupts = raw_interrupts & firq1_enable_reg;
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// The interrupts from the test registers module are not masked,
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// The interrupts from the test registers module are not masked,
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// just to keep their usage really simple
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// just to keep their usage really simple
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assign irq_0 = |{irq0_interrupts, i_test_reg_irq};
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assign irq_0 = |{irq0_interrupts, i_test_reg_irq};
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assign firq_0 = |{firq0_interrupts, i_test_reg_firq};
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assign firq_0 = |{firq0_interrupts, i_test_reg_firq};
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assign irq_1 = |irq1_interrupts;
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assign irq_1 = |irq1_interrupts;
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assign firq_1 = |firq1_interrupts;
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assign firq_1 = |firq1_interrupts;
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assign o_irq = irq_0 | irq_1;
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assign o_irq = irq_0 | irq_1;
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assign o_firq = firq_0 | firq_1;
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assign o_firq = firq_0 | firq_1;
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// ========================================================
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// ========================================================
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// Register Writes
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// Register Writes
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// ========================================================
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// ========================================================
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always @( posedge i_clk )
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always @( posedge i_clk )
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if ( wb_start_write )
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if ( wb_start_write )
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case ( i_wb_adr[15:0] )
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case ( i_wb_adr[15:0] )
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AMBER_IC_IRQ0_ENABLESET: irq0_enable_reg <= irq0_enable_reg | ( i_wb_dat);
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AMBER_IC_IRQ0_ENABLESET: irq0_enable_reg <= irq0_enable_reg | ( i_wb_dat);
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AMBER_IC_IRQ0_ENABLECLR: irq0_enable_reg <= irq0_enable_reg & (~i_wb_dat);
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AMBER_IC_IRQ0_ENABLECLR: irq0_enable_reg <= irq0_enable_reg & (~i_wb_dat);
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AMBER_IC_FIRQ0_ENABLESET: firq0_enable_reg <= firq0_enable_reg | ( i_wb_dat);
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AMBER_IC_FIRQ0_ENABLESET: firq0_enable_reg <= firq0_enable_reg | ( i_wb_dat);
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AMBER_IC_FIRQ0_ENABLECLR: firq0_enable_reg <= firq0_enable_reg & (~i_wb_dat);
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AMBER_IC_FIRQ0_ENABLECLR: firq0_enable_reg <= firq0_enable_reg & (~i_wb_dat);
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AMBER_IC_INT_SOFTSET_0: softint_0_reg <= softint_0_reg | ( i_wb_dat[0]);
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AMBER_IC_INT_SOFTSET_0: softint_0_reg <= softint_0_reg | ( i_wb_dat[0]);
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AMBER_IC_INT_SOFTCLEAR_0: softint_0_reg <= softint_0_reg & (~i_wb_dat[0]);
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AMBER_IC_INT_SOFTCLEAR_0: softint_0_reg <= softint_0_reg & (~i_wb_dat[0]);
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AMBER_IC_IRQ1_ENABLESET: irq1_enable_reg <= irq1_enable_reg | ( i_wb_dat);
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AMBER_IC_IRQ1_ENABLESET: irq1_enable_reg <= irq1_enable_reg | ( i_wb_dat);
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AMBER_IC_IRQ1_ENABLECLR: irq1_enable_reg <= irq1_enable_reg & (~i_wb_dat);
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AMBER_IC_IRQ1_ENABLECLR: irq1_enable_reg <= irq1_enable_reg & (~i_wb_dat);
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AMBER_IC_FIRQ1_ENABLESET: firq1_enable_reg <= firq1_enable_reg | ( i_wb_dat);
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AMBER_IC_FIRQ1_ENABLESET: firq1_enable_reg <= firq1_enable_reg | ( i_wb_dat);
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AMBER_IC_FIRQ1_ENABLECLR: firq1_enable_reg <= firq1_enable_reg & (~i_wb_dat);
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AMBER_IC_FIRQ1_ENABLECLR: firq1_enable_reg <= firq1_enable_reg & (~i_wb_dat);
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AMBER_IC_INT_SOFTSET_1: softint_1_reg <= softint_1_reg | ( i_wb_dat[0]);
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AMBER_IC_INT_SOFTSET_1: softint_1_reg <= softint_1_reg | ( i_wb_dat[0]);
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AMBER_IC_INT_SOFTCLEAR_1: softint_1_reg <= softint_1_reg & (~i_wb_dat[0]);
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AMBER_IC_INT_SOFTCLEAR_1: softint_1_reg <= softint_1_reg & (~i_wb_dat[0]);
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endcase
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endcase
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// ========================================================
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// ========================================================
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// Register Reads
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// Register Reads
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// ========================================================
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// ========================================================
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always @( posedge i_clk )
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always @( posedge i_clk )
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if ( wb_start_read )
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if ( wb_start_read )
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case ( i_wb_adr[15:0] )
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case ( i_wb_adr[15:0] )
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AMBER_IC_IRQ0_ENABLESET: wb_rdata <= irq0_enable_reg;
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AMBER_IC_IRQ0_ENABLESET: wb_rdata32 <= irq0_enable_reg;
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AMBER_IC_FIRQ0_ENABLESET: wb_rdata <= firq0_enable_reg;
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AMBER_IC_FIRQ0_ENABLESET: wb_rdata32 <= firq0_enable_reg;
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AMBER_IC_IRQ0_RAWSTAT: wb_rdata <= raw_interrupts;
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AMBER_IC_IRQ0_RAWSTAT: wb_rdata32 <= raw_interrupts;
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AMBER_IC_IRQ0_STATUS: wb_rdata <= irq0_interrupts;
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AMBER_IC_IRQ0_STATUS: wb_rdata32 <= irq0_interrupts;
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AMBER_IC_FIRQ0_RAWSTAT: wb_rdata <= raw_interrupts;
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AMBER_IC_FIRQ0_RAWSTAT: wb_rdata32 <= raw_interrupts;
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AMBER_IC_FIRQ0_STATUS: wb_rdata <= firq0_interrupts;
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AMBER_IC_FIRQ0_STATUS: wb_rdata32 <= firq0_interrupts;
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AMBER_IC_INT_SOFTSET_0: wb_rdata <= {31'd0, softint_0_reg};
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AMBER_IC_INT_SOFTSET_0: wb_rdata32 <= {31'd0, softint_0_reg};
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AMBER_IC_INT_SOFTCLEAR_0: wb_rdata <= {31'd0, softint_0_reg};
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AMBER_IC_INT_SOFTCLEAR_0: wb_rdata32 <= {31'd0, softint_0_reg};
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AMBER_IC_IRQ1_ENABLESET: wb_rdata <= irq1_enable_reg;
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AMBER_IC_IRQ1_ENABLESET: wb_rdata32 <= irq1_enable_reg;
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AMBER_IC_FIRQ1_ENABLESET: wb_rdata <= firq1_enable_reg;
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AMBER_IC_FIRQ1_ENABLESET: wb_rdata32 <= firq1_enable_reg;
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AMBER_IC_IRQ1_RAWSTAT: wb_rdata <= raw_interrupts;
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AMBER_IC_IRQ1_RAWSTAT: wb_rdata32 <= raw_interrupts;
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AMBER_IC_IRQ1_STATUS: wb_rdata <= irq1_interrupts;
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AMBER_IC_IRQ1_STATUS: wb_rdata32 <= irq1_interrupts;
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AMBER_IC_FIRQ1_RAWSTAT: wb_rdata <= raw_interrupts;
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AMBER_IC_FIRQ1_RAWSTAT: wb_rdata32 <= raw_interrupts;
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AMBER_IC_FIRQ1_STATUS: wb_rdata <= firq1_interrupts;
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AMBER_IC_FIRQ1_STATUS: wb_rdata32 <= firq1_interrupts;
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AMBER_IC_INT_SOFTSET_1: wb_rdata <= {31'd0, softint_1_reg};
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AMBER_IC_INT_SOFTSET_1: wb_rdata32 <= {31'd0, softint_1_reg};
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AMBER_IC_INT_SOFTCLEAR_1: wb_rdata <= {31'd0, softint_1_reg};
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AMBER_IC_INT_SOFTCLEAR_1: wb_rdata32 <= {31'd0, softint_1_reg};
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default: wb_rdata <= 32'h22334455;
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default: wb_rdata32 <= 32'h22334455;
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endcase
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endcase
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// =======================================================================================
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// =======================================================================================
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// =======================================================================================
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// =======================================================================================
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// =======================================================================================
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// =======================================================================================
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// Non-synthesizable debug code
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// Non-synthesizable debug code
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// =======================================================================================
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// =======================================================================================
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//synopsys translate_off
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//synopsys translate_off
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`ifdef AMBER_IC_DEBUG
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`ifdef AMBER_IC_DEBUG
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wire wb_read_ack = i_wb_stb && ( wb_start_write || wb_start_read_d1 );
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wire wb_read_ack = i_wb_stb && ( wb_start_write || wb_start_read_d1 );
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// -----------------------------------------------
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// -----------------------------------------------
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// Report Interrupt Controller Register accesses
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// Report Interrupt Controller Register accesses
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// -----------------------------------------------
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// -----------------------------------------------
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ( wb_read_ack || wb_start_write )
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if ( wb_read_ack || wb_start_write )
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begin
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begin
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`TB_DEBUG_MESSAGE
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`TB_DEBUG_MESSAGE
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if ( wb_start_write )
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if ( wb_start_write )
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$write("Write 0x%08x to ", i_wb_dat);
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$write("Write 0x%08x to ", i_wb_dat);
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else
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else
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$write("Read 0x%08x from ", o_wb_dat);
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$write("Read 0x%08x from ", o_wb_dat);
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case ( i_wb_adr[15:0] )
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case ( i_wb_adr[15:0] )
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AMBER_IC_IRQ0_STATUS:
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AMBER_IC_IRQ0_STATUS:
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$write(" Interrupt Controller module IRQ0 Status");
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$write(" Interrupt Controller module IRQ0 Status");
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AMBER_IC_IRQ0_RAWSTAT:
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AMBER_IC_IRQ0_RAWSTAT:
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$write(" Interrupt Controller module IRQ0 Raw Status");
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$write(" Interrupt Controller module IRQ0 Raw Status");
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AMBER_IC_IRQ0_ENABLESET:
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AMBER_IC_IRQ0_ENABLESET:
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$write(" Interrupt Controller module IRQ0 Enable Set");
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$write(" Interrupt Controller module IRQ0 Enable Set");
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AMBER_IC_IRQ0_ENABLECLR:
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AMBER_IC_IRQ0_ENABLECLR:
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$write(" Interrupt Controller module IRQ0 Enable Clear");
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$write(" Interrupt Controller module IRQ0 Enable Clear");
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AMBER_IC_FIRQ0_STATUS:
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AMBER_IC_FIRQ0_STATUS:
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$write(" Interrupt Controller module FIRQ0 Status");
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$write(" Interrupt Controller module FIRQ0 Status");
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AMBER_IC_FIRQ0_RAWSTAT:
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AMBER_IC_FIRQ0_RAWSTAT:
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$write(" Interrupt Controller module FIRQ0 Raw Status");
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$write(" Interrupt Controller module FIRQ0 Raw Status");
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AMBER_IC_FIRQ0_ENABLESET:
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AMBER_IC_FIRQ0_ENABLESET:
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$write(" Interrupt Controller module FIRQ0 Enable set");
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$write(" Interrupt Controller module FIRQ0 Enable set");
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AMBER_IC_FIRQ0_ENABLECLR:
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AMBER_IC_FIRQ0_ENABLECLR:
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$write(" Interrupt Controller module FIRQ0 Enable Clear");
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$write(" Interrupt Controller module FIRQ0 Enable Clear");
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AMBER_IC_INT_SOFTSET_0:
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AMBER_IC_INT_SOFTSET_0:
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$write(" Interrupt Controller module SoftInt 0 Set");
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$write(" Interrupt Controller module SoftInt 0 Set");
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AMBER_IC_INT_SOFTCLEAR_0:
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AMBER_IC_INT_SOFTCLEAR_0:
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$write(" Interrupt Controller module SoftInt 0 Clear");
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$write(" Interrupt Controller module SoftInt 0 Clear");
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AMBER_IC_IRQ1_STATUS:
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AMBER_IC_IRQ1_STATUS:
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$write(" Interrupt Controller module IRQ1 Status");
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$write(" Interrupt Controller module IRQ1 Status");
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AMBER_IC_IRQ1_RAWSTAT:
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AMBER_IC_IRQ1_RAWSTAT:
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$write(" Interrupt Controller module IRQ1 Raw Status");
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$write(" Interrupt Controller module IRQ1 Raw Status");
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AMBER_IC_IRQ1_ENABLESET:
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AMBER_IC_IRQ1_ENABLESET:
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$write(" Interrupt Controller module IRQ1 Enable Set");
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$write(" Interrupt Controller module IRQ1 Enable Set");
|
AMBER_IC_IRQ1_ENABLECLR:
|
AMBER_IC_IRQ1_ENABLECLR:
|
$write(" Interrupt Controller module IRQ1 Enable Clear");
|
$write(" Interrupt Controller module IRQ1 Enable Clear");
|
AMBER_IC_FIRQ1_STATUS:
|
AMBER_IC_FIRQ1_STATUS:
|
$write(" Interrupt Controller module FIRQ1 Status");
|
$write(" Interrupt Controller module FIRQ1 Status");
|
AMBER_IC_FIRQ1_RAWSTAT:
|
AMBER_IC_FIRQ1_RAWSTAT:
|
$write(" Interrupt Controller module FIRQ1 Raw Status");
|
$write(" Interrupt Controller module FIRQ1 Raw Status");
|
AMBER_IC_FIRQ1_ENABLESET:
|
AMBER_IC_FIRQ1_ENABLESET:
|
$write(" Interrupt Controller module FIRQ1 Enable set");
|
$write(" Interrupt Controller module FIRQ1 Enable set");
|
AMBER_IC_FIRQ1_ENABLECLR:
|
AMBER_IC_FIRQ1_ENABLECLR:
|
$write(" Interrupt Controller module FIRQ1 Enable Clear");
|
$write(" Interrupt Controller module FIRQ1 Enable Clear");
|
AMBER_IC_INT_SOFTSET_1:
|
AMBER_IC_INT_SOFTSET_1:
|
$write(" Interrupt Controller module SoftInt 1 Set");
|
$write(" Interrupt Controller module SoftInt 1 Set");
|
AMBER_IC_INT_SOFTCLEAR_1:
|
AMBER_IC_INT_SOFTCLEAR_1:
|
$write(" Interrupt Controller module SoftInt 1 Clear");
|
$write(" Interrupt Controller module SoftInt 1 Clear");
|
|
|
default:
|
default:
|
begin
|
begin
|
$write(" unknown Amber IC Register region");
|
$write(" unknown Amber IC Register region");
|
$write(", Address 0x%08h\n", i_wb_adr);
|
$write(", Address 0x%08h\n", i_wb_adr);
|
`TB_ERROR_MESSAGE
|
`TB_ERROR_MESSAGE
|
end
|
end
|
endcase
|
endcase
|
|
|
$write(", Address 0x%08h\n", i_wb_adr);
|
$write(", Address 0x%08h\n", i_wb_adr);
|
end
|
end
|
`endif
|
`endif
|
|
|
//synopsys translate_on
|
//synopsys translate_on
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|
