//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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// //
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// //
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// Top-level module instantiating the entire Amber 2 system. //
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// Top-level module instantiating the entire Amber 2 system. //
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// //
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// //
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// This file is part of the Amber project //
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// This file is part of the Amber project //
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// http://www.opencores.org/project,amber //
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// http://www.opencores.org/project,amber //
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// //
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// //
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// Description //
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// Description //
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// This is the highest level synthesizable module in the //
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// This is the highest level synthesizable module in the //
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// project. The ports in this module represent pins on the //
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// project. The ports in this module represent pins on the //
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// FPGA. //
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// FPGA. //
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// //
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// //
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// Author(s): //
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// Author(s): //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// //
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// //
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//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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// //
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// //
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// Copyright (C) 2010 Authors and OPENCORES.ORG //
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// Copyright (C) 2010 Authors and OPENCORES.ORG //
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// //
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// //
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// This source file may be used and distributed without //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// the original copyright notice and the associated disclaimer. //
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// //
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// //
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// This source file is free software; you can redistribute it //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// later version. //
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// //
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// //
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// This source is distributed in the hope that it will be //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// details. //
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// //
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// //
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// You should have received a copy of the GNU Lesser General //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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// //
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//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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module system
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module system
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(
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(
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input brd_rst,
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input brd_rst,
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input brd_clk_n,
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input brd_clk_n,
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input brd_clk_p,
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input brd_clk_p,
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`ifdef XILINX_VIRTEX6_FPGA
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`ifdef XILINX_VIRTEX6_FPGA
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input sys_clk_p,
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input sys_clk_p,
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input sys_clk_n,
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input sys_clk_n,
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`endif
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`endif
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// UART 0 Interface
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// UART 0 Interface
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input i_uart0_rts,
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input i_uart0_rts,
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output o_uart0_rx,
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output o_uart0_rx,
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output o_uart0_cts,
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output o_uart0_cts,
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input i_uart0_tx,
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input i_uart0_tx,
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|
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// Xilinx Spartan 6 MCB DDR3 Interface
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// Xilinx Spartan 6 MCB DDR3 Interface
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inout [15:0] ddr3_dq,
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inout [15:0] ddr3_dq,
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output [12:0] ddr3_addr,
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output [12:0] ddr3_addr,
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output [2:0] ddr3_ba,
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output [2:0] ddr3_ba,
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output ddr3_ras_n,
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output ddr3_ras_n,
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output ddr3_cas_n,
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output ddr3_cas_n,
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output ddr3_we_n,
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output ddr3_we_n,
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output ddr3_odt,
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output ddr3_odt,
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output ddr3_reset_n,
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output ddr3_reset_n,
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output ddr3_cke,
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output ddr3_cke,
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output [1:0] ddr3_dm,
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output [1:0] ddr3_dm,
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inout [1:0] ddr3_dqs_p,
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inout [1:0] ddr3_dqs_p,
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inout [1:0] ddr3_dqs_n,
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inout [1:0] ddr3_dqs_n,
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output ddr3_ck_p,
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output ddr3_ck_p,
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output ddr3_ck_n,
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output ddr3_ck_n,
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`ifdef XILINX_VIRTEX6_FPGA
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`ifdef XILINX_VIRTEX6_FPGA
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output ddr3_cs_n,
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output ddr3_cs_n,
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`endif
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`endif
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`ifdef XILINX_SPARTAN6_FPGA
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`ifdef XILINX_SPARTAN6_FPGA
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inout mcb3_rzq,
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inout mcb3_rzq,
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inout mcb3_zio,
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inout mcb3_zio,
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`endif
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`endif
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// Ethmac B100 MAC to PHY Interface
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// Ethmac B100 MAC to PHY Interface
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input mtx_clk_pad_i,
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input mtx_clk_pad_i,
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output [3:0] mtxd_pad_o,
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output [3:0] mtxd_pad_o,
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output mtxen_pad_o,
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output mtxen_pad_o,
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output mtxerr_pad_o,
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output mtxerr_pad_o,
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input mrx_clk_pad_i,
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input mrx_clk_pad_i,
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input [3:0] mrxd_pad_i,
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input [3:0] mrxd_pad_i,
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input mrxdv_pad_i,
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input mrxdv_pad_i,
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input mrxerr_pad_i,
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input mrxerr_pad_i,
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input mcoll_pad_i,
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input mcoll_pad_i,
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input mcrs_pad_i,
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input mcrs_pad_i,
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inout md_pad_io,
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inout md_pad_io,
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output mdc_pad_o,
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output mdc_pad_o,
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output phy_reset_n
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output phy_reset_n
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);
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);
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wire sys_clk; // System clock
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wire sys_clk; // System clock
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wire sys_rst; // Active low reset, synchronous to sys_clk
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wire sys_rst; // Active low reset, synchronous to sys_clk
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wire clk_200; // 200MHz from board
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wire clk_200; // 200MHz from board
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// ======================================
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// ======================================
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// Xilinx MCB DDR3 Controller connections
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// Xilinx MCB DDR3 Controller connections
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// ======================================
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// ======================================
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`ifdef XILINX_SPARTAN6_FPGA
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`ifdef XILINX_SPARTAN6_FPGA
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wire c3_p0_cmd_en;
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wire c3_p0_cmd_en;
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wire [2:0] c3_p0_cmd_instr;
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wire [2:0] c3_p0_cmd_instr;
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wire [29:0] c3_p0_cmd_byte_addr;
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wire [29:0] c3_p0_cmd_byte_addr;
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wire c3_p0_wr_en;
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wire c3_p0_wr_en;
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wire [15:0] c3_p0_wr_mask;
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wire [15:0] c3_p0_wr_mask;
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wire [127:0] c3_p0_wr_data;
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wire [127:0] c3_p0_wr_data;
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wire [127:0] c3_p0_rd_data;
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wire [127:0] c3_p0_rd_data;
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wire c3_p0_rd_empty;
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wire c3_p0_rd_empty;
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wire c3_p0_cmd_full;
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wire c3_p0_cmd_full;
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wire c3_p0_wr_full;
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wire c3_p0_wr_full;
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`endif
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`endif
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wire phy_init_done;
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wire phy_init_done;
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wire test_mem_ctrl;
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wire test_mem_ctrl;
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wire system_rdy;
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wire system_rdy;
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// ======================================
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// ======================================
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// Xilinx Virtex-6 DDR3 Controller connections
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// Xilinx Virtex-6 DDR3 Controller connections
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// ======================================
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// ======================================
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`ifdef XILINX_VIRTEX6_FPGA
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`ifdef XILINX_VIRTEX6_FPGA
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wire phy_init_done1;
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wire phy_init_done1;
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wire xv6_cmd_en;
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wire xv6_cmd_en;
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wire [2:0] xv6_cmd_instr;
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wire [2:0] xv6_cmd_instr;
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wire [26:0] xv6_cmd_byte_addr;
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wire [26:0] xv6_cmd_byte_addr;
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wire xv6_cmd_full;
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wire xv6_cmd_full;
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wire xv6_wr_full;
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wire xv6_wr_full;
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wire xv6_wr_en;
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wire xv6_wr_en;
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wire xv6_wr_end;
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wire xv6_wr_end;
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wire [7:0] xv6_wr_mask;
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wire [7:0] xv6_wr_mask;
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wire [63:0] xv6_wr_data;
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wire [63:0] xv6_wr_data;
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wire [63:0] xv6_rd_data;
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wire [63:0] xv6_rd_data;
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wire xv6_rd_data_valid;
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wire xv6_rd_data_valid;
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wire xv6_ddr3_clk;
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wire xv6_ddr3_clk;
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`endif
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`endif
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// ======================================
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// ======================================
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// Ethmac MII
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// Ethmac MII
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// ======================================
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// ======================================
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wire md_pad_i;
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wire md_pad_i;
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wire md_pad_o;
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wire md_pad_o;
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wire md_padoe_o;
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wire md_padoe_o;
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// ======================================
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// ======================================
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// Wishbone Buses
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// Wishbone Buses
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// ======================================
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// ======================================
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localparam WB_MASTERS = 2;
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localparam WB_MASTERS = 2;
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localparam WB_SLAVES = 9;
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localparam WB_SLAVES = 9;
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`ifdef AMBER_A25_CORE
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localparam WB_DWIDTH = 128;
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localparam WB_SWIDTH = 16;
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`else
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localparam WB_DWIDTH = 32;
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localparam WB_SWIDTH = 4;
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`endif
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// Wishbone Master Buses
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// Wishbone Master Buses
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wire [31:0] m_wb_adr [WB_MASTERS-1:0];
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wire [31:0] m_wb_adr [WB_MASTERS-1:0];
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wire [3:0] m_wb_sel [WB_MASTERS-1:0];
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wire [WB_SWIDTH-1:0] m_wb_sel [WB_MASTERS-1:0];
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wire [WB_MASTERS-1:0] m_wb_we ;
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wire [WB_MASTERS-1:0] m_wb_we ;
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wire [31:0] m_wb_dat_w [WB_MASTERS-1:0];
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wire [WB_DWIDTH-1:0] m_wb_dat_w [WB_MASTERS-1:0];
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wire [31:0] m_wb_dat_r [WB_MASTERS-1:0];
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wire [WB_DWIDTH-1:0] m_wb_dat_r [WB_MASTERS-1:0];
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wire [WB_MASTERS-1:0] m_wb_cyc ;
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wire [WB_MASTERS-1:0] m_wb_cyc ;
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wire [WB_MASTERS-1:0] m_wb_stb ;
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wire [WB_MASTERS-1:0] m_wb_stb ;
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wire [WB_MASTERS-1:0] m_wb_ack ;
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wire [WB_MASTERS-1:0] m_wb_ack ;
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wire [WB_MASTERS-1:0] m_wb_err ;
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wire [WB_MASTERS-1:0] m_wb_err ;
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// Wishbone Slave Buses
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// Wishbone Slave Buses
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wire [31:0] s_wb_adr [WB_SLAVES-1:0];
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wire [31:0] s_wb_adr [WB_SLAVES-1:0];
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wire [3:0] s_wb_sel [WB_SLAVES-1:0];
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wire [WB_SWIDTH-1:0] s_wb_sel [WB_SLAVES-1:0];
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wire [WB_SLAVES-1:0] s_wb_we ;
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wire [WB_SLAVES-1:0] s_wb_we ;
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wire [31:0] s_wb_dat_w [WB_SLAVES-1:0];
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wire [WB_DWIDTH-1:0] s_wb_dat_w [WB_SLAVES-1:0];
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wire [31:0] s_wb_dat_r [WB_SLAVES-1:0];
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wire [WB_DWIDTH-1:0] s_wb_dat_r [WB_SLAVES-1:0];
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wire [WB_SLAVES-1:0] s_wb_cyc ;
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wire [WB_SLAVES-1:0] s_wb_cyc ;
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wire [WB_SLAVES-1:0] s_wb_stb ;
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wire [WB_SLAVES-1:0] s_wb_stb ;
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wire [WB_SLAVES-1:0] s_wb_ack ;
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wire [WB_SLAVES-1:0] s_wb_ack ;
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wire [WB_SLAVES-1:0] s_wb_err ;
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wire [WB_SLAVES-1:0] s_wb_err ;
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wire [31:0] emm_wb_adr;
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wire [3:0] emm_wb_sel;
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wire emm_wb_we;
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wire [31:0] emm_wb_rdat;
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wire [31:0] emm_wb_wdat;
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wire emm_wb_cyc;
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wire emm_wb_stb;
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wire emm_wb_ack;
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wire emm_wb_err;
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wire [31:0] ems_wb_adr;
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wire [3:0] ems_wb_sel;
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wire ems_wb_we;
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wire [31:0] ems_wb_rdat;
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wire [31:0] ems_wb_wdat;
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wire ems_wb_cyc;
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wire ems_wb_stb;
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wire ems_wb_ack;
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wire ems_wb_err;
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// ======================================
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// ======================================
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// Interrupts
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// Interrupts
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// ======================================
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// ======================================
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wire amber_irq;
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wire amber_irq;
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wire amber_firq;
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wire amber_firq;
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wire ethmac_int;
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wire ethmac_int;
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wire test_reg_irq;
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wire test_reg_irq;
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wire test_reg_firq;
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wire test_reg_firq;
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wire uart0_int;
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wire uart0_int;
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wire uart1_int;
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wire uart1_int;
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wire [2:0] timer_int;
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wire [2:0] timer_int;
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// ======================================
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// ======================================
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// Clocks and Resets Module
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// Clocks and Resets Module
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// ======================================
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// ======================================
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clocks_resets u_clocks_resets (
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clocks_resets u_clocks_resets (
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.i_brd_rst ( brd_rst ),
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.i_brd_rst ( brd_rst ),
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.i_brd_clk_n ( brd_clk_n ),
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.i_brd_clk_n ( brd_clk_n ),
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.i_brd_clk_p ( brd_clk_p ),
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.i_brd_clk_p ( brd_clk_p ),
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.i_ddr_calib_done ( phy_init_done ),
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.i_ddr_calib_done ( phy_init_done ),
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.o_sys_rst ( sys_rst ),
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.o_sys_rst ( sys_rst ),
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.o_sys_clk ( sys_clk ),
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.o_sys_clk ( sys_clk ),
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.o_clk_200 ( clk_200 )
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.o_clk_200 ( clk_200 )
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);
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);
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// -------------------------------------------------------------
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// -------------------------------------------------------------
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// Instantiate Amber Processor Core
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// Instantiate Amber Processor Core
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// -------------------------------------------------------------
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// -------------------------------------------------------------
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`ifdef AMBER_A25_CORE
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`ifdef AMBER_A25_CORE
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a25_core u_amber (
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a25_core u_amber (
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`else
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`else
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a23_core u_amber (
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a23_core u_amber (
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`endif
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`endif
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.i_clk ( sys_clk ),
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.i_clk ( sys_clk ),
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|
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.i_irq ( amber_irq ),
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.i_irq ( amber_irq ),
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.i_firq ( amber_firq ),
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.i_firq ( amber_firq ),
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|
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.i_system_rdy ( system_rdy ),
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.i_system_rdy ( system_rdy ),
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|
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.o_wb_adr ( m_wb_adr [1] ),
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.o_wb_adr ( m_wb_adr [1] ),
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.o_wb_sel ( m_wb_sel [1] ),
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.o_wb_sel ( m_wb_sel [1] ),
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.o_wb_we ( m_wb_we [1] ),
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.o_wb_we ( m_wb_we [1] ),
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.i_wb_dat ( m_wb_dat_r[1] ),
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.i_wb_dat ( m_wb_dat_r[1] ),
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.o_wb_dat ( m_wb_dat_w[1] ),
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.o_wb_dat ( m_wb_dat_w[1] ),
|
.o_wb_cyc ( m_wb_cyc [1] ),
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.o_wb_cyc ( m_wb_cyc [1] ),
|
.o_wb_stb ( m_wb_stb [1] ),
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.o_wb_stb ( m_wb_stb [1] ),
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.i_wb_ack ( m_wb_ack [1] ),
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.i_wb_ack ( m_wb_ack [1] ),
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.i_wb_err ( m_wb_err [1] )
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.i_wb_err ( m_wb_err [1] )
|
);
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);
|
|
|
|
|
// -------------------------------------------------------------
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// -------------------------------------------------------------
|
// Instantiate B100 Ethernet MAC
|
// Instantiate B100 Ethernet MAC
|
// -------------------------------------------------------------
|
// -------------------------------------------------------------
|
|
|
eth_top u_eth_top (
|
eth_top u_eth_top (
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.wb_clk_i ( sys_clk ),
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.wb_clk_i ( sys_clk ),
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.wb_rst_i ( sys_rst ),
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.wb_rst_i ( sys_rst ),
|
|
|
// WISHBONE slave
|
// WISHBONE slave
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.wb_adr_i ( s_wb_adr [0][11:2] ),
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.wb_adr_i ( ems_wb_adr [11:2] ),
|
.wb_sel_i ( s_wb_sel [0] ),
|
.wb_sel_i ( ems_wb_sel ),
|
.wb_we_i ( s_wb_we [0] ),
|
.wb_we_i ( ems_wb_we ),
|
.wb_cyc_i ( s_wb_cyc [0] ),
|
.wb_cyc_i ( ems_wb_cyc ),
|
.wb_stb_i ( s_wb_stb [0] ),
|
.wb_stb_i ( ems_wb_stb ),
|
.wb_ack_o ( s_wb_ack [0] ),
|
.wb_ack_o ( ems_wb_ack ),
|
.wb_dat_i ( s_wb_dat_w [0] ),
|
.wb_dat_i ( ems_wb_wdat ),
|
.wb_dat_o ( s_wb_dat_r [0] ),
|
.wb_dat_o ( ems_wb_rdat ),
|
.wb_err_o ( s_wb_err [0] ),
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.wb_err_o ( ems_wb_err ),
|
|
|
// WISHBONE master
|
// WISHBONE master
|
.m_wb_adr_o ( m_wb_adr [0] ),
|
.m_wb_adr_o ( emm_wb_adr ),
|
.m_wb_sel_o ( m_wb_sel [0] ),
|
.m_wb_sel_o ( emm_wb_sel ),
|
.m_wb_we_o ( m_wb_we [0] ),
|
.m_wb_we_o ( emm_wb_we ),
|
.m_wb_dat_i ( m_wb_dat_r [0] ),
|
.m_wb_dat_i ( emm_wb_rdat ),
|
.m_wb_dat_o ( m_wb_dat_w [0] ),
|
.m_wb_dat_o ( emm_wb_wdat ),
|
.m_wb_cyc_o ( m_wb_cyc [0] ),
|
.m_wb_cyc_o ( emm_wb_cyc ),
|
.m_wb_stb_o ( m_wb_stb [0] ),
|
.m_wb_stb_o ( emm_wb_stb ),
|
.m_wb_ack_i ( m_wb_ack [0] ),
|
.m_wb_ack_i ( emm_wb_ack ),
|
.m_wb_err_i ( m_wb_err [0] ),
|
.m_wb_err_i ( emm_wb_err ),
|
|
|
// MAC to PHY I/F
|
// MAC to PHY I/F
|
.mtx_clk_pad_i ( mtx_clk_pad_i ),
|
.mtx_clk_pad_i ( mtx_clk_pad_i ),
|
.mtxd_pad_o ( mtxd_pad_o ),
|
.mtxd_pad_o ( mtxd_pad_o ),
|
.mtxen_pad_o ( mtxen_pad_o ),
|
.mtxen_pad_o ( mtxen_pad_o ),
|
.mtxerr_pad_o ( mtxerr_pad_o ),
|
.mtxerr_pad_o ( mtxerr_pad_o ),
|
.mrx_clk_pad_i ( mrx_clk_pad_i ),
|
.mrx_clk_pad_i ( mrx_clk_pad_i ),
|
.mrxd_pad_i ( mrxd_pad_i ),
|
.mrxd_pad_i ( mrxd_pad_i ),
|
.mrxdv_pad_i ( mrxdv_pad_i ),
|
.mrxdv_pad_i ( mrxdv_pad_i ),
|
.mrxerr_pad_i ( mrxerr_pad_i ),
|
.mrxerr_pad_i ( mrxerr_pad_i ),
|
.mcoll_pad_i ( mcoll_pad_i ),
|
.mcoll_pad_i ( mcoll_pad_i ),
|
.mcrs_pad_i ( mcrs_pad_i ),
|
.mcrs_pad_i ( mcrs_pad_i ),
|
.md_pad_i ( md_pad_i ),
|
.md_pad_i ( md_pad_i ),
|
.mdc_pad_o ( mdc_pad_o ),
|
.mdc_pad_o ( mdc_pad_o ),
|
.md_pad_o ( md_pad_o ),
|
.md_pad_o ( md_pad_o ),
|
.md_padoe_o ( md_padoe_o ),
|
.md_padoe_o ( md_padoe_o ),
|
|
|
// Interrupt
|
// Interrupt
|
.int_o ( ethmac_int )
|
.int_o ( ethmac_int )
|
);
|
);
|
|
|
|
|
|
|
// -------------------------------------------------------------
|
// -------------------------------------------------------------
|
// Instantiate Ethernet Control Interface tri-state buffer
|
// Instantiate Ethernet Control Interface tri-state buffer
|
// -------------------------------------------------------------
|
// -------------------------------------------------------------
|
`ifdef XILINX_FPGA
|
`ifdef XILINX_FPGA
|
IOBUF u_iobuf (
|
IOBUF u_iobuf (
|
`else
|
`else
|
generic_iobuf u_iobuf (
|
generic_iobuf u_iobuf (
|
`endif
|
`endif
|
.O ( md_pad_i ),
|
.O ( md_pad_i ),
|
.IO ( md_pad_io ),
|
.IO ( md_pad_io ),
|
.I ( md_pad_o ),
|
.I ( md_pad_o ),
|
// T is high for tri-state output
|
// T is high for tri-state output
|
.T ( ~md_padoe_o )
|
.T ( ~md_padoe_o )
|
);
|
);
|
|
|
// Ethernet MII PHY reset
|
// Ethernet MII PHY reset
|
assign phy_reset_n = !sys_rst;
|
assign phy_reset_n = !sys_rst;
|
|
|
// Halt core until system is ready
|
// Halt core until system is ready
|
assign system_rdy = phy_init_done && !sys_rst;
|
assign system_rdy = phy_init_done && !sys_rst;
|
|
|
// -------------------------------------------------------------
|
// -------------------------------------------------------------
|
// Instantiate Boot Memory - 8KBytes of Embedded SRAM
|
// Instantiate Boot Memory - 8KBytes of Embedded SRAM
|
// -------------------------------------------------------------
|
// -------------------------------------------------------------
|
boot_mem u_boot_mem (
|
boot_mem #(
|
|
.WB_DWIDTH ( WB_DWIDTH ),
|
|
.WB_SWIDTH ( WB_SWIDTH )
|
|
)
|
|
u_boot_mem (
|
.i_wb_clk ( sys_clk ),
|
.i_wb_clk ( sys_clk ),
|
|
|
.i_wb_adr ( s_wb_adr [1] ),
|
.i_wb_adr ( s_wb_adr [1] ),
|
.i_wb_sel ( s_wb_sel [1] ),
|
.i_wb_sel ( s_wb_sel [1] ),
|
.i_wb_we ( s_wb_we [1] ),
|
.i_wb_we ( s_wb_we [1] ),
|
.o_wb_dat ( s_wb_dat_r[1] ),
|
.o_wb_dat ( s_wb_dat_r[1] ),
|
.i_wb_dat ( s_wb_dat_w[1] ),
|
.i_wb_dat ( s_wb_dat_w[1] ),
|
.i_wb_cyc ( s_wb_cyc [1] ),
|
.i_wb_cyc ( s_wb_cyc [1] ),
|
.i_wb_stb ( s_wb_stb [1] ),
|
.i_wb_stb ( s_wb_stb [1] ),
|
.o_wb_ack ( s_wb_ack [1] ),
|
.o_wb_ack ( s_wb_ack [1] ),
|
.o_wb_err ( s_wb_err [1] )
|
.o_wb_err ( s_wb_err [1] )
|
);
|
);
|
|
|
|
|
|
|
// -------------------------------------------------------------
|
// -------------------------------------------------------------
|
// Instantiate UART0
|
// Instantiate UART0
|
// -------------------------------------------------------------
|
// -------------------------------------------------------------
|
uart u_uart0 (
|
uart #(
|
|
.WB_DWIDTH ( WB_DWIDTH ),
|
|
.WB_SWIDTH ( WB_SWIDTH )
|
|
)
|
|
u_uart0 (
|
.i_clk ( sys_clk ),
|
.i_clk ( sys_clk ),
|
|
|
.o_uart_int ( uart0_int ),
|
.o_uart_int ( uart0_int ),
|
|
|
.i_uart_cts_n ( i_uart0_rts ),
|
.i_uart_cts_n ( i_uart0_rts ),
|
.o_uart_txd ( o_uart0_rx ),
|
.o_uart_txd ( o_uart0_rx ),
|
.o_uart_rts_n ( o_uart0_cts ),
|
.o_uart_rts_n ( o_uart0_cts ),
|
.i_uart_rxd ( i_uart0_tx ),
|
.i_uart_rxd ( i_uart0_tx ),
|
|
|
.i_wb_adr ( s_wb_adr [3] ),
|
.i_wb_adr ( s_wb_adr [3] ),
|
.i_wb_sel ( s_wb_sel [3] ),
|
.i_wb_sel ( s_wb_sel [3] ),
|
.i_wb_we ( s_wb_we [3] ),
|
.i_wb_we ( s_wb_we [3] ),
|
.o_wb_dat ( s_wb_dat_r[3] ),
|
.o_wb_dat ( s_wb_dat_r[3] ),
|
.i_wb_dat ( s_wb_dat_w[3] ),
|
.i_wb_dat ( s_wb_dat_w[3] ),
|
.i_wb_cyc ( s_wb_cyc [3] ),
|
.i_wb_cyc ( s_wb_cyc [3] ),
|
.i_wb_stb ( s_wb_stb [3] ),
|
.i_wb_stb ( s_wb_stb [3] ),
|
.o_wb_ack ( s_wb_ack [3] ),
|
.o_wb_ack ( s_wb_ack [3] ),
|
.o_wb_err ( s_wb_err [3] )
|
.o_wb_err ( s_wb_err [3] )
|
);
|
);
|
|
|
|
|
// -------------------------------------------------------------
|
// -------------------------------------------------------------
|
// Instantiate UART1
|
// Instantiate UART1
|
// -------------------------------------------------------------
|
// -------------------------------------------------------------
|
uart u_uart1 (
|
uart #(
|
|
.WB_DWIDTH ( WB_DWIDTH ),
|
|
.WB_SWIDTH ( WB_SWIDTH )
|
|
)
|
|
u_uart1 (
|
.i_clk ( sys_clk ),
|
.i_clk ( sys_clk ),
|
|
|
.o_uart_int ( uart1_int ),
|
.o_uart_int ( uart1_int ),
|
|
|
// These are not connected. ONly pins for 1 UART
|
// These are not connected. ONly pins for 1 UART
|
// on my development board
|
// on my development board
|
.i_uart_cts_n ( 1'd1 ),
|
.i_uart_cts_n ( 1'd1 ),
|
.o_uart_txd ( ),
|
.o_uart_txd ( ),
|
.o_uart_rts_n ( ),
|
.o_uart_rts_n ( ),
|
.i_uart_rxd ( 1'd1 ),
|
.i_uart_rxd ( 1'd1 ),
|
|
|
.i_wb_adr ( s_wb_adr [4] ),
|
.i_wb_adr ( s_wb_adr [4] ),
|
.i_wb_sel ( s_wb_sel [4] ),
|
.i_wb_sel ( s_wb_sel [4] ),
|
.i_wb_we ( s_wb_we [4] ),
|
.i_wb_we ( s_wb_we [4] ),
|
.o_wb_dat ( s_wb_dat_r[4] ),
|
.o_wb_dat ( s_wb_dat_r[4] ),
|
.i_wb_dat ( s_wb_dat_w[4] ),
|
.i_wb_dat ( s_wb_dat_w[4] ),
|
.i_wb_cyc ( s_wb_cyc [4] ),
|
.i_wb_cyc ( s_wb_cyc [4] ),
|
.i_wb_stb ( s_wb_stb [4] ),
|
.i_wb_stb ( s_wb_stb [4] ),
|
.o_wb_ack ( s_wb_ack [4] ),
|
.o_wb_ack ( s_wb_ack [4] ),
|
.o_wb_err ( s_wb_err [4] )
|
.o_wb_err ( s_wb_err [4] )
|
);
|
);
|
|
|
|
|
// -------------------------------------------------------------
|
// -------------------------------------------------------------
|
// Instantiate Test Module
|
// Instantiate Test Module
|
// - includes register used to terminate tests
|
// - includes register used to terminate tests
|
// -------------------------------------------------------------
|
// -------------------------------------------------------------
|
test_module u_test_module (
|
test_module #(
|
|
.WB_DWIDTH ( WB_DWIDTH ),
|
|
.WB_SWIDTH ( WB_SWIDTH )
|
|
)
|
|
u_test_module (
|
.i_clk ( sys_clk ),
|
.i_clk ( sys_clk ),
|
|
|
.o_irq ( test_reg_irq ),
|
.o_irq ( test_reg_irq ),
|
.o_firq ( test_reg_firq ),
|
.o_firq ( test_reg_firq ),
|
.o_mem_ctrl ( test_mem_ctrl ),
|
.o_mem_ctrl ( test_mem_ctrl ),
|
.i_wb_adr ( s_wb_adr [5] ),
|
.i_wb_adr ( s_wb_adr [5] ),
|
.i_wb_sel ( s_wb_sel [5] ),
|
.i_wb_sel ( s_wb_sel [5] ),
|
.i_wb_we ( s_wb_we [5] ),
|
.i_wb_we ( s_wb_we [5] ),
|
.o_wb_dat ( s_wb_dat_r[5] ),
|
.o_wb_dat ( s_wb_dat_r[5] ),
|
.i_wb_dat ( s_wb_dat_w[5] ),
|
.i_wb_dat ( s_wb_dat_w[5] ),
|
.i_wb_cyc ( s_wb_cyc [5] ),
|
.i_wb_cyc ( s_wb_cyc [5] ),
|
.i_wb_stb ( s_wb_stb [5] ),
|
.i_wb_stb ( s_wb_stb [5] ),
|
.o_wb_ack ( s_wb_ack [5] ),
|
.o_wb_ack ( s_wb_ack [5] ),
|
.o_wb_err ( s_wb_err [5] )
|
.o_wb_err ( s_wb_err [5] )
|
);
|
);
|
|
|
|
|
// -------------------------------------------------------------
|
// -------------------------------------------------------------
|
// Instantiate Timer Module
|
// Instantiate Timer Module
|
// -------------------------------------------------------------
|
// -------------------------------------------------------------
|
timer_module u_timer_module (
|
timer_module #(
|
|
.WB_DWIDTH ( WB_DWIDTH ),
|
|
.WB_SWIDTH ( WB_SWIDTH )
|
|
)
|
|
u_timer_module (
|
.i_clk ( sys_clk ),
|
.i_clk ( sys_clk ),
|
|
|
// Interrupt outputs
|
// Interrupt outputs
|
.o_timer_int ( timer_int ),
|
.o_timer_int ( timer_int ),
|
|
|
// Wishbone interface
|
// Wishbone interface
|
.i_wb_adr ( s_wb_adr [6] ),
|
.i_wb_adr ( s_wb_adr [6] ),
|
.i_wb_sel ( s_wb_sel [6] ),
|
.i_wb_sel ( s_wb_sel [6] ),
|
.i_wb_we ( s_wb_we [6] ),
|
.i_wb_we ( s_wb_we [6] ),
|
.o_wb_dat ( s_wb_dat_r[6] ),
|
.o_wb_dat ( s_wb_dat_r[6] ),
|
.i_wb_dat ( s_wb_dat_w[6] ),
|
.i_wb_dat ( s_wb_dat_w[6] ),
|
.i_wb_cyc ( s_wb_cyc [6] ),
|
.i_wb_cyc ( s_wb_cyc [6] ),
|
.i_wb_stb ( s_wb_stb [6] ),
|
.i_wb_stb ( s_wb_stb [6] ),
|
.o_wb_ack ( s_wb_ack [6] ),
|
.o_wb_ack ( s_wb_ack [6] ),
|
.o_wb_err ( s_wb_err [6] )
|
.o_wb_err ( s_wb_err [6] )
|
);
|
);
|
|
|
|
|
// -------------------------------------------------------------
|
// -------------------------------------------------------------
|
// Instantiate Interrupt Controller Module
|
// Instantiate Interrupt Controller Module
|
// -------------------------------------------------------------
|
// -------------------------------------------------------------
|
interrupt_controller u_interrupt_controller (
|
interrupt_controller #(
|
|
.WB_DWIDTH ( WB_DWIDTH ),
|
|
.WB_SWIDTH ( WB_SWIDTH )
|
|
)
|
|
u_interrupt_controller (
|
.i_clk ( sys_clk ),
|
.i_clk ( sys_clk ),
|
|
|
// Interrupt outputs
|
// Interrupt outputs
|
.o_irq ( amber_irq ),
|
.o_irq ( amber_irq ),
|
.o_firq ( amber_firq ),
|
.o_firq ( amber_firq ),
|
|
|
// Interrupt inputs
|
// Interrupt inputs
|
.i_uart0_int ( uart0_int ),
|
.i_uart0_int ( uart0_int ),
|
.i_uart1_int ( uart1_int ),
|
.i_uart1_int ( uart1_int ),
|
.i_ethmac_int ( ethmac_int ),
|
.i_ethmac_int ( ethmac_int ),
|
.i_test_reg_irq ( test_reg_irq ),
|
.i_test_reg_irq ( test_reg_irq ),
|
.i_test_reg_firq ( test_reg_firq ),
|
.i_test_reg_firq ( test_reg_firq ),
|
.i_tm_timer_int ( timer_int ),
|
.i_tm_timer_int ( timer_int ),
|
|
|
// Wishbone interface
|
// Wishbone interface
|
.i_wb_adr ( s_wb_adr [7] ),
|
.i_wb_adr ( s_wb_adr [7] ),
|
.i_wb_sel ( s_wb_sel [7] ),
|
.i_wb_sel ( s_wb_sel [7] ),
|
.i_wb_we ( s_wb_we [7] ),
|
.i_wb_we ( s_wb_we [7] ),
|
.o_wb_dat ( s_wb_dat_r[7] ),
|
.o_wb_dat ( s_wb_dat_r[7] ),
|
.i_wb_dat ( s_wb_dat_w[7] ),
|
.i_wb_dat ( s_wb_dat_w[7] ),
|
.i_wb_cyc ( s_wb_cyc [7] ),
|
.i_wb_cyc ( s_wb_cyc [7] ),
|
.i_wb_stb ( s_wb_stb [7] ),
|
.i_wb_stb ( s_wb_stb [7] ),
|
.o_wb_ack ( s_wb_ack [7] ),
|
.o_wb_ack ( s_wb_ack [7] ),
|
.o_wb_err ( s_wb_err [7] )
|
.o_wb_err ( s_wb_err [7] )
|
);
|
);
|
|
|
|
|
|
|
|
|
`ifndef XILINX_FPGA
|
`ifndef XILINX_FPGA
|
// ======================================
|
// ======================================
|
// Instantiate non-synthesizable main memory model
|
// Instantiate non-synthesizable main memory model
|
// ======================================
|
// ======================================
|
|
|
assign phy_init_done = 1'd1;
|
assign phy_init_done = 1'd1;
|
|
|
main_mem u_main_mem (
|
main_mem #(
|
|
.WB_DWIDTH ( WB_DWIDTH ),
|
|
.WB_SWIDTH ( WB_SWIDTH )
|
|
)
|
|
u_main_mem (
|
.i_clk ( sys_clk ),
|
.i_clk ( sys_clk ),
|
.i_mem_ctrl ( test_mem_ctrl ),
|
.i_mem_ctrl ( test_mem_ctrl ),
|
.i_wb_adr ( s_wb_adr [2] ),
|
.i_wb_adr ( s_wb_adr [2] ),
|
.i_wb_sel ( s_wb_sel [2] ),
|
.i_wb_sel ( s_wb_sel [2] ),
|
.i_wb_we ( s_wb_we [2] ),
|
.i_wb_we ( s_wb_we [2] ),
|
.o_wb_dat ( s_wb_dat_r[2] ),
|
.o_wb_dat ( s_wb_dat_r[2] ),
|
.i_wb_dat ( s_wb_dat_w[2] ),
|
.i_wb_dat ( s_wb_dat_w[2] ),
|
.i_wb_cyc ( s_wb_cyc [2] ),
|
.i_wb_cyc ( s_wb_cyc [2] ),
|
.i_wb_stb ( s_wb_stb [2] ),
|
.i_wb_stb ( s_wb_stb [2] ),
|
.o_wb_ack ( s_wb_ack [2] ),
|
.o_wb_ack ( s_wb_ack [2] ),
|
.o_wb_err ( s_wb_err [2] )
|
.o_wb_err ( s_wb_err [2] )
|
);
|
);
|
|
|
`endif
|
`endif
|
|
|
|
|
`ifdef XILINX_SPARTAN6_FPGA
|
`ifdef XILINX_SPARTAN6_FPGA
|
// -------------------------------------------------------------
|
// -------------------------------------------------------------
|
// Instantiate Wishbone to Xilinx Spartan-6 DDR3 Bridge
|
// Instantiate Wishbone to Xilinx Spartan-6 DDR3 Bridge
|
// -------------------------------------------------------------
|
// -------------------------------------------------------------
|
// The clock crossing fifo for spartan-6 is build into the mcb
|
// The clock crossing fifo for spartan-6 is build into the mcb
|
wb_xs6_ddr3_bridge u_wb_xs6_ddr3_bridge (
|
wb_xs6_ddr3_bridge u_wb_xs6_ddr3_bridge (
|
.i_clk ( sys_clk ),
|
.i_clk ( sys_clk ),
|
|
|
.o_cmd_en ( c3_p0_cmd_en ),
|
.o_cmd_en ( c3_p0_cmd_en ),
|
.o_cmd_instr ( c3_p0_cmd_instr ),
|
.o_cmd_instr ( c3_p0_cmd_instr ),
|
.o_cmd_byte_addr ( c3_p0_cmd_byte_addr ),
|
.o_cmd_byte_addr ( c3_p0_cmd_byte_addr ),
|
.i_cmd_full ( c3_p0_cmd_full ),
|
.i_cmd_full ( c3_p0_cmd_full ),
|
.i_wr_full ( c3_p0_wr_full ),
|
.i_wr_full ( c3_p0_wr_full ),
|
.o_wr_en ( c3_p0_wr_en ),
|
.o_wr_en ( c3_p0_wr_en ),
|
.o_wr_mask ( c3_p0_wr_mask ),
|
.o_wr_mask ( c3_p0_wr_mask ),
|
.o_wr_data ( c3_p0_wr_data ),
|
.o_wr_data ( c3_p0_wr_data ),
|
.i_rd_data ( c3_p0_rd_data ),
|
.i_rd_data ( c3_p0_rd_data ),
|
.i_rd_empty ( c3_p0_rd_empty ),
|
.i_rd_empty ( c3_p0_rd_empty ),
|
|
|
.i_mem_ctrl ( test_mem_ctrl ),
|
.i_mem_ctrl ( test_mem_ctrl ),
|
.i_wb_adr ( s_wb_adr [2] ),
|
.i_wb_adr ( s_wb_adr [2] ),
|
.i_wb_sel ( s_wb_sel [2] ),
|
.i_wb_sel ( s_wb_sel [2] ),
|
.i_wb_we ( s_wb_we [2] ),
|
.i_wb_we ( s_wb_we [2] ),
|
.o_wb_dat ( s_wb_dat_r[2] ),
|
.o_wb_dat ( s_wb_dat_r[2] ),
|
.i_wb_dat ( s_wb_dat_w[2] ),
|
.i_wb_dat ( s_wb_dat_w[2] ),
|
.i_wb_cyc ( s_wb_cyc [2] ),
|
.i_wb_cyc ( s_wb_cyc [2] ),
|
.i_wb_stb ( s_wb_stb [2] ),
|
.i_wb_stb ( s_wb_stb [2] ),
|
.o_wb_ack ( s_wb_ack [2] ),
|
.o_wb_ack ( s_wb_ack [2] ),
|
.o_wb_err ( s_wb_err [2] )
|
.o_wb_err ( s_wb_err [2] )
|
);
|
);
|
|
|
|
|
// -------------------------------------------------------------
|
// -------------------------------------------------------------
|
// Instantiate Xilinx Spartan-6 FPGA MCB-DDR3 Controller
|
// Instantiate Xilinx Spartan-6 FPGA MCB-DDR3 Controller
|
// -------------------------------------------------------------
|
// -------------------------------------------------------------
|
mcb_ddr3 u_mcb_ddr3 (
|
mcb_ddr3 u_mcb_ddr3 (
|
|
|
// DDR3 signals
|
// DDR3 signals
|
.mcb3_dram_dq ( ddr3_dq ),
|
.mcb3_dram_dq ( ddr3_dq ),
|
.mcb3_dram_a ( ddr3_addr ),
|
.mcb3_dram_a ( ddr3_addr ),
|
.mcb3_dram_ba ( ddr3_ba ),
|
.mcb3_dram_ba ( ddr3_ba ),
|
.mcb3_dram_ras_n ( ddr3_ras_n ),
|
.mcb3_dram_ras_n ( ddr3_ras_n ),
|
.mcb3_dram_cas_n ( ddr3_cas_n ),
|
.mcb3_dram_cas_n ( ddr3_cas_n ),
|
.mcb3_dram_we_n ( ddr3_we_n ),
|
.mcb3_dram_we_n ( ddr3_we_n ),
|
.mcb3_dram_odt ( ddr3_odt ),
|
.mcb3_dram_odt ( ddr3_odt ),
|
.mcb3_dram_reset_n ( ddr3_reset_n ),
|
.mcb3_dram_reset_n ( ddr3_reset_n ),
|
.mcb3_dram_cke ( ddr3_cke ),
|
.mcb3_dram_cke ( ddr3_cke ),
|
.mcb3_dram_udm ( ddr3_dm[1] ),
|
.mcb3_dram_udm ( ddr3_dm[1] ),
|
.mcb3_dram_dm ( ddr3_dm[0] ),
|
.mcb3_dram_dm ( ddr3_dm[0] ),
|
.mcb3_rzq ( mcb3_rzq ),
|
.mcb3_rzq ( mcb3_rzq ),
|
.mcb3_zio ( mcb3_zio ),
|
.mcb3_zio ( mcb3_zio ),
|
.mcb3_dram_udqs ( ddr3_dqs_p[1] ),
|
.mcb3_dram_udqs ( ddr3_dqs_p[1] ),
|
.mcb3_dram_dqs ( ddr3_dqs_p[0] ),
|
.mcb3_dram_dqs ( ddr3_dqs_p[0] ),
|
.mcb3_dram_udqs_n ( ddr3_dqs_n[1] ),
|
.mcb3_dram_udqs_n ( ddr3_dqs_n[1] ),
|
.mcb3_dram_dqs_n ( ddr3_dqs_n[0] ),
|
.mcb3_dram_dqs_n ( ddr3_dqs_n[0] ),
|
.mcb3_dram_ck ( ddr3_ck_p ),
|
.mcb3_dram_ck ( ddr3_ck_p ),
|
.mcb3_dram_ck_n ( ddr3_ck_n ),
|
.mcb3_dram_ck_n ( ddr3_ck_n ),
|
|
|
.sys_clk_ibufg ( clk_200 ),
|
.sys_clk_ibufg ( clk_200 ),
|
.c3_sys_rst_n ( brd_rst ),
|
.c3_sys_rst_n ( brd_rst ),
|
|
|
.c3_calib_done ( phy_init_done ),
|
.c3_calib_done ( phy_init_done ),
|
|
|
.c3_p0_cmd_clk ( sys_clk ),
|
.c3_p0_cmd_clk ( sys_clk ),
|
|
|
.c3_p0_cmd_en ( c3_p0_cmd_en ),
|
.c3_p0_cmd_en ( c3_p0_cmd_en ),
|
.c3_p0_cmd_instr ( c3_p0_cmd_instr ),
|
.c3_p0_cmd_instr ( c3_p0_cmd_instr ),
|
.c3_p0_cmd_bl ( 6'd0 ),
|
.c3_p0_cmd_bl ( 6'd0 ),
|
.c3_p0_cmd_byte_addr ( c3_p0_cmd_byte_addr ),
|
.c3_p0_cmd_byte_addr ( c3_p0_cmd_byte_addr ),
|
.c3_p0_cmd_empty ( ),
|
.c3_p0_cmd_empty ( ),
|
.c3_p0_cmd_full ( c3_p0_cmd_full ),
|
.c3_p0_cmd_full ( c3_p0_cmd_full ),
|
|
|
.c3_p0_wr_clk ( sys_clk ),
|
.c3_p0_wr_clk ( sys_clk ),
|
|
|
.c3_p0_wr_en ( c3_p0_wr_en ),
|
.c3_p0_wr_en ( c3_p0_wr_en ),
|
.c3_p0_wr_mask ( c3_p0_wr_mask ),
|
.c3_p0_wr_mask ( c3_p0_wr_mask ),
|
.c3_p0_wr_data ( c3_p0_wr_data ),
|
.c3_p0_wr_data ( c3_p0_wr_data ),
|
.c3_p0_wr_full ( c3_p0_wr_full ),
|
.c3_p0_wr_full ( c3_p0_wr_full ),
|
.c3_p0_wr_empty ( ),
|
.c3_p0_wr_empty ( ),
|
.c3_p0_wr_count ( ),
|
.c3_p0_wr_count ( ),
|
.c3_p0_wr_underrun ( ),
|
.c3_p0_wr_underrun ( ),
|
.c3_p0_wr_error ( ),
|
.c3_p0_wr_error ( ),
|
|
|
.c3_p0_rd_clk ( sys_clk ),
|
.c3_p0_rd_clk ( sys_clk ),
|
|
|
.c3_p0_rd_en ( 1'd1 ),
|
.c3_p0_rd_en ( 1'd1 ),
|
.c3_p0_rd_data ( c3_p0_rd_data ),
|
.c3_p0_rd_data ( c3_p0_rd_data ),
|
.c3_p0_rd_full ( ),
|
.c3_p0_rd_full ( ),
|
.c3_p0_rd_empty ( c3_p0_rd_empty ),
|
.c3_p0_rd_empty ( c3_p0_rd_empty ),
|
.c3_p0_rd_count ( ),
|
.c3_p0_rd_count ( ),
|
.c3_p0_rd_overflow ( ),
|
.c3_p0_rd_overflow ( ),
|
.c3_p0_rd_error ( )
|
.c3_p0_rd_error ( )
|
);
|
);
|
`endif
|
`endif
|
|
|
|
|
`ifdef XILINX_VIRTEX6_FPGA
|
`ifdef XILINX_VIRTEX6_FPGA
|
// -------------------------------------------------------------
|
// -------------------------------------------------------------
|
// Instantiate Wishbone to Xilinx Spartan-6 DDR3 Bridge
|
// Instantiate Wishbone to Xilinx Spartan-6 DDR3 Bridge
|
// -------------------------------------------------------------
|
// -------------------------------------------------------------
|
// The clock crossing fifo for virtex-6 is insode the bridge
|
// The clock crossing fifo for virtex-6 is insode the bridge
|
// module
|
// module
|
wb_xv6_ddr3_bridge u_wb_xv6_ddr3_bridge (
|
wb_xv6_ddr3_bridge u_wb_xv6_ddr3_bridge (
|
.i_sys_clk ( sys_clk ),
|
.i_sys_clk ( sys_clk ),
|
.i_ddr_clk ( xv6_ddr3_clk ),
|
.i_ddr_clk ( xv6_ddr3_clk ),
|
|
|
.o_ddr_cmd_en ( xv6_cmd_en ),
|
.o_ddr_cmd_en ( xv6_cmd_en ),
|
.o_ddr_cmd_instr ( xv6_cmd_instr ),
|
.o_ddr_cmd_instr ( xv6_cmd_instr ),
|
.o_ddr_cmd_byte_addr ( xv6_cmd_byte_addr ),
|
.o_ddr_cmd_byte_addr ( xv6_cmd_byte_addr ),
|
.i_ddr_cmd_full ( xv6_cmd_full ),
|
.i_ddr_cmd_full ( xv6_cmd_full ),
|
|
|
.i_ddr_wr_full ( xv6_wr_full ),
|
.i_ddr_wr_full ( xv6_wr_full ),
|
.o_ddr_wr_en ( xv6_wr_en ),
|
.o_ddr_wr_en ( xv6_wr_en ),
|
.o_ddr_wr_end ( xv6_wr_end ),
|
.o_ddr_wr_end ( xv6_wr_end ),
|
.o_ddr_wr_mask ( xv6_wr_mask ),
|
.o_ddr_wr_mask ( xv6_wr_mask ),
|
.o_ddr_wr_data ( xv6_wr_data ),
|
.o_ddr_wr_data ( xv6_wr_data ),
|
|
|
.i_ddr_rd_data ( xv6_rd_data ),
|
.i_ddr_rd_data ( xv6_rd_data ),
|
.i_ddr_rd_valid ( xv6_rd_data_valid ),
|
.i_ddr_rd_valid ( xv6_rd_data_valid ),
|
|
|
.i_phy_init_done ( phy_init_done1 ),
|
.i_phy_init_done ( phy_init_done1 ),
|
.o_phy_init_done ( phy_init_done ), // delayed version
|
.o_phy_init_done ( phy_init_done ), // delayed version
|
|
|
.i_mem_ctrl ( test_mem_ctrl ),
|
.i_mem_ctrl ( test_mem_ctrl ),
|
.i_wb_adr ( s_wb_adr [2] ),
|
.i_wb_adr ( s_wb_adr [2] ),
|
.i_wb_sel ( s_wb_sel [2] ),
|
.i_wb_sel ( s_wb_sel [2] ),
|
.i_wb_we ( s_wb_we [2] ),
|
.i_wb_we ( s_wb_we [2] ),
|
.o_wb_dat ( s_wb_dat_r[2] ),
|
.o_wb_dat ( s_wb_dat_r[2] ),
|
.i_wb_dat ( s_wb_dat_w[2] ),
|
.i_wb_dat ( s_wb_dat_w[2] ),
|
.i_wb_cyc ( s_wb_cyc [2] ),
|
.i_wb_cyc ( s_wb_cyc [2] ),
|
.i_wb_stb ( s_wb_stb [2] ),
|
.i_wb_stb ( s_wb_stb [2] ),
|
.o_wb_ack ( s_wb_ack [2] ),
|
.o_wb_ack ( s_wb_ack [2] ),
|
.o_wb_err ( s_wb_err [2] )
|
.o_wb_err ( s_wb_err [2] )
|
);
|
);
|
|
|
|
|
// -------------------------------------------------------------
|
// -------------------------------------------------------------
|
// Instantiate Xilinx Virtex-6 FPGA DDR3 Controller
|
// Instantiate Xilinx Virtex-6 FPGA DDR3 Controller
|
// -------------------------------------------------------------
|
// -------------------------------------------------------------
|
xv6_ddr3
|
xv6_ddr3
|
#( // - Skip the memory initilization sequence,
|
#( // - Skip the memory initilization sequence,
|
.SIM_INIT_OPTION ("SKIP_PU_DLY" ),
|
.SIM_INIT_OPTION ("SKIP_PU_DLY" ),
|
// - Skip the delay Calibration process
|
// - Skip the delay Calibration process
|
.SIM_CAL_OPTION ("FAST_CAL" ),
|
.SIM_CAL_OPTION ("FAST_CAL" ),
|
.RST_ACT_LOW ( 0 )
|
.RST_ACT_LOW ( 0 )
|
)
|
)
|
u_xv6_ddr3 (
|
u_xv6_ddr3 (
|
// DDR3 signals
|
// DDR3 signals
|
.ddr3_dq ( ddr3_dq ),
|
.ddr3_dq ( ddr3_dq ),
|
.ddr3_addr ( ddr3_addr ),
|
.ddr3_addr ( ddr3_addr ),
|
.ddr3_ba ( ddr3_ba ),
|
.ddr3_ba ( ddr3_ba ),
|
.ddr3_ras_n ( ddr3_ras_n ),
|
.ddr3_ras_n ( ddr3_ras_n ),
|
.ddr3_cas_n ( ddr3_cas_n ),
|
.ddr3_cas_n ( ddr3_cas_n ),
|
.ddr3_we_n ( ddr3_we_n ),
|
.ddr3_we_n ( ddr3_we_n ),
|
.ddr3_odt ( ddr3_odt ),
|
.ddr3_odt ( ddr3_odt ),
|
.ddr3_reset_n ( ddr3_reset_n ),
|
.ddr3_reset_n ( ddr3_reset_n ),
|
.ddr3_cke ( ddr3_cke ),
|
.ddr3_cke ( ddr3_cke ),
|
.ddr3_dm ( ddr3_dm ),
|
.ddr3_dm ( ddr3_dm ),
|
.ddr3_dqs_p ( ddr3_dqs_p ),
|
.ddr3_dqs_p ( ddr3_dqs_p ),
|
.ddr3_dqs_n ( ddr3_dqs_n ),
|
.ddr3_dqs_n ( ddr3_dqs_n ),
|
.ddr3_ck_p ( ddr3_ck_p ),
|
.ddr3_ck_p ( ddr3_ck_p ),
|
.ddr3_ck_n ( ddr3_ck_n ),
|
.ddr3_ck_n ( ddr3_ck_n ),
|
.ddr3_cs_n ( ddr3_cs_n ),
|
.ddr3_cs_n ( ddr3_cs_n ),
|
|
|
// DDR clock
|
// DDR clock
|
.sys_clk_p ( sys_clk_p ),
|
.sys_clk_p ( sys_clk_p ),
|
.sys_clk_n ( sys_clk_n ),
|
.sys_clk_n ( sys_clk_n ),
|
.clk_ref ( clk_200 ),
|
.clk_ref ( clk_200 ),
|
.sys_rst ( brd_rst ),
|
.sys_rst ( brd_rst ),
|
.tb_rst ( ),
|
.tb_rst ( ),
|
.tb_clk ( xv6_ddr3_clk ),
|
.tb_clk ( xv6_ddr3_clk ),
|
.phy_init_done ( phy_init_done1 ),
|
.phy_init_done ( phy_init_done1 ),
|
|
|
.app_en ( xv6_cmd_en ),
|
.app_en ( xv6_cmd_en ),
|
.app_cmd ( xv6_cmd_instr ),
|
.app_cmd ( xv6_cmd_instr ),
|
.tg_addr ( xv6_cmd_byte_addr ),
|
.tg_addr ( xv6_cmd_byte_addr ),
|
.app_full ( xv6_cmd_full ),
|
.app_full ( xv6_cmd_full ),
|
|
|
.app_wdf_wren ( xv6_wr_en ),
|
.app_wdf_wren ( xv6_wr_en ),
|
.app_wdf_mask ( xv6_wr_mask ),
|
.app_wdf_mask ( xv6_wr_mask ),
|
.app_wdf_data ( xv6_wr_data ),
|
.app_wdf_data ( xv6_wr_data ),
|
.app_wdf_end ( xv6_wr_end ),
|
.app_wdf_end ( xv6_wr_end ),
|
.app_wdf_full ( xv6_wr_full ),
|
.app_wdf_full ( xv6_wr_full ),
|
|
|
.app_rd_data ( xv6_rd_data ),
|
.app_rd_data ( xv6_rd_data ),
|
.app_rd_data_valid ( xv6_rd_data_valid )
|
.app_rd_data_valid ( xv6_rd_data_valid )
|
);
|
);
|
|
|
`endif
|
`endif
|
|
|
|
|
|
|
// -------------------------------------------------------------
|
// -------------------------------------------------------------
|
// Instantiate Wishbone Arbiter
|
// Instantiate Wishbone Arbiter
|
// -------------------------------------------------------------
|
// -------------------------------------------------------------
|
wishbone_arbiter u_wishbone_arbiter (
|
wishbone_arbiter #(
|
|
.WB_DWIDTH ( WB_DWIDTH ),
|
|
.WB_SWIDTH ( WB_SWIDTH )
|
|
)
|
|
u_wishbone_arbiter (
|
.i_wb_clk ( sys_clk ),
|
.i_wb_clk ( sys_clk ),
|
|
|
// WISHBONE master 0 - Ethmac
|
// WISHBONE master 0 - Ethmac
|
.i_m0_wb_adr ( m_wb_adr [0] ),
|
.i_m0_wb_adr ( m_wb_adr [0] ),
|
.i_m0_wb_sel ( m_wb_sel [0] ),
|
.i_m0_wb_sel ( m_wb_sel [0] ),
|
.i_m0_wb_we ( m_wb_we [0] ),
|
.i_m0_wb_we ( m_wb_we [0] ),
|
.o_m0_wb_dat ( m_wb_dat_r [0] ),
|
.o_m0_wb_dat ( m_wb_dat_r [0] ),
|
.i_m0_wb_dat ( m_wb_dat_w [0] ),
|
.i_m0_wb_dat ( m_wb_dat_w [0] ),
|
.i_m0_wb_cyc ( m_wb_cyc [0] ),
|
.i_m0_wb_cyc ( m_wb_cyc [0] ),
|
.i_m0_wb_stb ( m_wb_stb [0] ),
|
.i_m0_wb_stb ( m_wb_stb [0] ),
|
.o_m0_wb_ack ( m_wb_ack [0] ),
|
.o_m0_wb_ack ( m_wb_ack [0] ),
|
.o_m0_wb_err ( m_wb_err [0] ),
|
.o_m0_wb_err ( m_wb_err [0] ),
|
|
|
|
|
// WISHBONE master 1 - Amber Process or
|
// WISHBONE master 1 - Amber Process or
|
.i_m1_wb_adr ( m_wb_adr [1] ),
|
.i_m1_wb_adr ( m_wb_adr [1] ),
|
.i_m1_wb_sel ( m_wb_sel [1] ),
|
.i_m1_wb_sel ( m_wb_sel [1] ),
|
.i_m1_wb_we ( m_wb_we [1] ),
|
.i_m1_wb_we ( m_wb_we [1] ),
|
.o_m1_wb_dat ( m_wb_dat_r [1] ),
|
.o_m1_wb_dat ( m_wb_dat_r [1] ),
|
.i_m1_wb_dat ( m_wb_dat_w [1] ),
|
.i_m1_wb_dat ( m_wb_dat_w [1] ),
|
.i_m1_wb_cyc ( m_wb_cyc [1] ),
|
.i_m1_wb_cyc ( m_wb_cyc [1] ),
|
.i_m1_wb_stb ( m_wb_stb [1] ),
|
.i_m1_wb_stb ( m_wb_stb [1] ),
|
.o_m1_wb_ack ( m_wb_ack [1] ),
|
.o_m1_wb_ack ( m_wb_ack [1] ),
|
.o_m1_wb_err ( m_wb_err [1] ),
|
.o_m1_wb_err ( m_wb_err [1] ),
|
|
|
|
|
// WISHBONE slave 0 - Ethmac
|
// WISHBONE slave 0 - Ethmac
|
.o_s0_wb_adr ( s_wb_adr [0] ),
|
.o_s0_wb_adr ( s_wb_adr [0] ),
|
.o_s0_wb_sel ( s_wb_sel [0] ),
|
.o_s0_wb_sel ( s_wb_sel [0] ),
|
.o_s0_wb_we ( s_wb_we [0] ),
|
.o_s0_wb_we ( s_wb_we [0] ),
|
.i_s0_wb_dat ( s_wb_dat_r [0] ),
|
.i_s0_wb_dat ( s_wb_dat_r [0] ),
|
.o_s0_wb_dat ( s_wb_dat_w [0] ),
|
.o_s0_wb_dat ( s_wb_dat_w [0] ),
|
.o_s0_wb_cyc ( s_wb_cyc [0] ),
|
.o_s0_wb_cyc ( s_wb_cyc [0] ),
|
.o_s0_wb_stb ( s_wb_stb [0] ),
|
.o_s0_wb_stb ( s_wb_stb [0] ),
|
.i_s0_wb_ack ( s_wb_ack [0] ),
|
.i_s0_wb_ack ( s_wb_ack [0] ),
|
.i_s0_wb_err ( s_wb_err [0] ),
|
.i_s0_wb_err ( s_wb_err [0] ),
|
|
|
|
|
// WISHBONE slave 1 - Boot Memory
|
// WISHBONE slave 1 - Boot Memory
|
.o_s1_wb_adr ( s_wb_adr [1] ),
|
.o_s1_wb_adr ( s_wb_adr [1] ),
|
.o_s1_wb_sel ( s_wb_sel [1] ),
|
.o_s1_wb_sel ( s_wb_sel [1] ),
|
.o_s1_wb_we ( s_wb_we [1] ),
|
.o_s1_wb_we ( s_wb_we [1] ),
|
.i_s1_wb_dat ( s_wb_dat_r [1] ),
|
.i_s1_wb_dat ( s_wb_dat_r [1] ),
|
.o_s1_wb_dat ( s_wb_dat_w [1] ),
|
.o_s1_wb_dat ( s_wb_dat_w [1] ),
|
.o_s1_wb_cyc ( s_wb_cyc [1] ),
|
.o_s1_wb_cyc ( s_wb_cyc [1] ),
|
.o_s1_wb_stb ( s_wb_stb [1] ),
|
.o_s1_wb_stb ( s_wb_stb [1] ),
|
.i_s1_wb_ack ( s_wb_ack [1] ),
|
.i_s1_wb_ack ( s_wb_ack [1] ),
|
.i_s1_wb_err ( s_wb_err [1] ),
|
.i_s1_wb_err ( s_wb_err [1] ),
|
|
|
|
|
// WISHBONE slave 2 - Main Memory
|
// WISHBONE slave 2 - Main Memory
|
.o_s2_wb_adr ( s_wb_adr [2] ),
|
.o_s2_wb_adr ( s_wb_adr [2] ),
|
.o_s2_wb_sel ( s_wb_sel [2] ),
|
.o_s2_wb_sel ( s_wb_sel [2] ),
|
.o_s2_wb_we ( s_wb_we [2] ),
|
.o_s2_wb_we ( s_wb_we [2] ),
|
.i_s2_wb_dat ( s_wb_dat_r [2] ),
|
.i_s2_wb_dat ( s_wb_dat_r [2] ),
|
.o_s2_wb_dat ( s_wb_dat_w [2] ),
|
.o_s2_wb_dat ( s_wb_dat_w [2] ),
|
.o_s2_wb_cyc ( s_wb_cyc [2] ),
|
.o_s2_wb_cyc ( s_wb_cyc [2] ),
|
.o_s2_wb_stb ( s_wb_stb [2] ),
|
.o_s2_wb_stb ( s_wb_stb [2] ),
|
.i_s2_wb_ack ( s_wb_ack [2] ),
|
.i_s2_wb_ack ( s_wb_ack [2] ),
|
.i_s2_wb_err ( s_wb_err [2] ),
|
.i_s2_wb_err ( s_wb_err [2] ),
|
|
|
|
|
// WISHBONE slave 3 - UART 0
|
// WISHBONE slave 3 - UART 0
|
.o_s3_wb_adr ( s_wb_adr [3] ),
|
.o_s3_wb_adr ( s_wb_adr [3] ),
|
.o_s3_wb_sel ( s_wb_sel [3] ),
|
.o_s3_wb_sel ( s_wb_sel [3] ),
|
.o_s3_wb_we ( s_wb_we [3] ),
|
.o_s3_wb_we ( s_wb_we [3] ),
|
.i_s3_wb_dat ( s_wb_dat_r [3] ),
|
.i_s3_wb_dat ( s_wb_dat_r [3] ),
|
.o_s3_wb_dat ( s_wb_dat_w [3] ),
|
.o_s3_wb_dat ( s_wb_dat_w [3] ),
|
.o_s3_wb_cyc ( s_wb_cyc [3] ),
|
.o_s3_wb_cyc ( s_wb_cyc [3] ),
|
.o_s3_wb_stb ( s_wb_stb [3] ),
|
.o_s3_wb_stb ( s_wb_stb [3] ),
|
.i_s3_wb_ack ( s_wb_ack [3] ),
|
.i_s3_wb_ack ( s_wb_ack [3] ),
|
.i_s3_wb_err ( s_wb_err [3] ),
|
.i_s3_wb_err ( s_wb_err [3] ),
|
|
|
|
|
// WISHBONE slave 4 - UART 1
|
// WISHBONE slave 4 - UART 1
|
.o_s4_wb_adr ( s_wb_adr [4] ),
|
.o_s4_wb_adr ( s_wb_adr [4] ),
|
.o_s4_wb_sel ( s_wb_sel [4] ),
|
.o_s4_wb_sel ( s_wb_sel [4] ),
|
.o_s4_wb_we ( s_wb_we [4] ),
|
.o_s4_wb_we ( s_wb_we [4] ),
|
.i_s4_wb_dat ( s_wb_dat_r [4] ),
|
.i_s4_wb_dat ( s_wb_dat_r [4] ),
|
.o_s4_wb_dat ( s_wb_dat_w [4] ),
|
.o_s4_wb_dat ( s_wb_dat_w [4] ),
|
.o_s4_wb_cyc ( s_wb_cyc [4] ),
|
.o_s4_wb_cyc ( s_wb_cyc [4] ),
|
.o_s4_wb_stb ( s_wb_stb [4] ),
|
.o_s4_wb_stb ( s_wb_stb [4] ),
|
.i_s4_wb_ack ( s_wb_ack [4] ),
|
.i_s4_wb_ack ( s_wb_ack [4] ),
|
.i_s4_wb_err ( s_wb_err [4] ),
|
.i_s4_wb_err ( s_wb_err [4] ),
|
|
|
|
|
// WISHBONE slave 5 - Test Module
|
// WISHBONE slave 5 - Test Module
|
.o_s5_wb_adr ( s_wb_adr [5] ),
|
.o_s5_wb_adr ( s_wb_adr [5] ),
|
.o_s5_wb_sel ( s_wb_sel [5] ),
|
.o_s5_wb_sel ( s_wb_sel [5] ),
|
.o_s5_wb_we ( s_wb_we [5] ),
|
.o_s5_wb_we ( s_wb_we [5] ),
|
.i_s5_wb_dat ( s_wb_dat_r [5] ),
|
.i_s5_wb_dat ( s_wb_dat_r [5] ),
|
.o_s5_wb_dat ( s_wb_dat_w [5] ),
|
.o_s5_wb_dat ( s_wb_dat_w [5] ),
|
.o_s5_wb_cyc ( s_wb_cyc [5] ),
|
.o_s5_wb_cyc ( s_wb_cyc [5] ),
|
.o_s5_wb_stb ( s_wb_stb [5] ),
|
.o_s5_wb_stb ( s_wb_stb [5] ),
|
.i_s5_wb_ack ( s_wb_ack [5] ),
|
.i_s5_wb_ack ( s_wb_ack [5] ),
|
.i_s5_wb_err ( s_wb_err [5] ),
|
.i_s5_wb_err ( s_wb_err [5] ),
|
|
|
|
|
// WISHBONE slave 6 - Timer Module
|
// WISHBONE slave 6 - Timer Module
|
.o_s6_wb_adr ( s_wb_adr [6] ),
|
.o_s6_wb_adr ( s_wb_adr [6] ),
|
.o_s6_wb_sel ( s_wb_sel [6] ),
|
.o_s6_wb_sel ( s_wb_sel [6] ),
|
.o_s6_wb_we ( s_wb_we [6] ),
|
.o_s6_wb_we ( s_wb_we [6] ),
|
.i_s6_wb_dat ( s_wb_dat_r [6] ),
|
.i_s6_wb_dat ( s_wb_dat_r [6] ),
|
.o_s6_wb_dat ( s_wb_dat_w [6] ),
|
.o_s6_wb_dat ( s_wb_dat_w [6] ),
|
.o_s6_wb_cyc ( s_wb_cyc [6] ),
|
.o_s6_wb_cyc ( s_wb_cyc [6] ),
|
.o_s6_wb_stb ( s_wb_stb [6] ),
|
.o_s6_wb_stb ( s_wb_stb [6] ),
|
.i_s6_wb_ack ( s_wb_ack [6] ),
|
.i_s6_wb_ack ( s_wb_ack [6] ),
|
.i_s6_wb_err ( s_wb_err [6] ),
|
.i_s6_wb_err ( s_wb_err [6] ),
|
|
|
|
|
// WISHBONE slave 7 - Interrupt Controller
|
// WISHBONE slave 7 - Interrupt Controller
|
.o_s7_wb_adr ( s_wb_adr [7] ),
|
.o_s7_wb_adr ( s_wb_adr [7] ),
|
.o_s7_wb_sel ( s_wb_sel [7] ),
|
.o_s7_wb_sel ( s_wb_sel [7] ),
|
.o_s7_wb_we ( s_wb_we [7] ),
|
.o_s7_wb_we ( s_wb_we [7] ),
|
.i_s7_wb_dat ( s_wb_dat_r [7] ),
|
.i_s7_wb_dat ( s_wb_dat_r [7] ),
|
.o_s7_wb_dat ( s_wb_dat_w [7] ),
|
.o_s7_wb_dat ( s_wb_dat_w [7] ),
|
.o_s7_wb_cyc ( s_wb_cyc [7] ),
|
.o_s7_wb_cyc ( s_wb_cyc [7] ),
|
.o_s7_wb_stb ( s_wb_stb [7] ),
|
.o_s7_wb_stb ( s_wb_stb [7] ),
|
.i_s7_wb_ack ( s_wb_ack [7] ),
|
.i_s7_wb_ack ( s_wb_ack [7] ),
|
.i_s7_wb_err ( s_wb_err [7] )
|
.i_s7_wb_err ( s_wb_err [7] )
|
);
|
);
|
|
|
|
|
|
ethmac_wb #(
|
|
.WB_DWIDTH ( WB_DWIDTH ),
|
|
.WB_SWIDTH ( WB_SWIDTH )
|
|
)
|
|
u_ethmac_wb (
|
|
// Wishbone arbiter side
|
|
.o_m_wb_adr ( m_wb_adr [0] ),
|
|
.o_m_wb_sel ( m_wb_sel [0] ),
|
|
.o_m_wb_we ( m_wb_we [0] ),
|
|
.i_m_wb_rdat ( m_wb_dat_r [0] ),
|
|
.o_m_wb_wdat ( m_wb_dat_w [0] ),
|
|
.o_m_wb_cyc ( m_wb_cyc [0] ),
|
|
.o_m_wb_stb ( m_wb_stb [0] ),
|
|
.i_m_wb_ack ( m_wb_ack [0] ),
|
|
.i_m_wb_err ( m_wb_err [0] ),
|
|
|
|
// Wishbone arbiter side
|
|
.i_s_wb_adr ( s_wb_adr [0] ),
|
|
.i_s_wb_sel ( s_wb_sel [0] ),
|
|
.i_s_wb_we ( s_wb_we [0] ),
|
|
.i_s_wb_cyc ( s_wb_cyc [0] ),
|
|
.i_s_wb_stb ( s_wb_stb [0] ),
|
|
.o_s_wb_ack ( s_wb_ack [0] ),
|
|
.i_s_wb_wdat ( s_wb_dat_w [0] ),
|
|
.o_s_wb_rdat ( s_wb_dat_r [0] ),
|
|
.o_s_wb_err ( s_wb_err [0] ),
|
|
|
|
// Ethmac side
|
|
.i_m_wb_adr ( emm_wb_adr ),
|
|
.i_m_wb_sel ( emm_wb_sel ),
|
|
.i_m_wb_we ( emm_wb_we ),
|
|
.o_m_wb_rdat ( emm_wb_rdat ),
|
|
.i_m_wb_wdat ( emm_wb_wdat ),
|
|
.i_m_wb_cyc ( emm_wb_cyc ),
|
|
.i_m_wb_stb ( emm_wb_stb ),
|
|
.o_m_wb_ack ( emm_wb_ack ),
|
|
.o_m_wb_err ( emm_wb_err ),
|
|
|
|
// Ethmac side
|
|
.o_s_wb_adr ( ems_wb_adr ),
|
|
.o_s_wb_sel ( ems_wb_sel ),
|
|
.o_s_wb_we ( ems_wb_we ),
|
|
.i_s_wb_rdat ( ems_wb_rdat ),
|
|
.o_s_wb_wdat ( ems_wb_wdat ),
|
|
.o_s_wb_cyc ( ems_wb_cyc ),
|
|
.o_s_wb_stb ( ems_wb_stb ),
|
|
.i_s_wb_ack ( ems_wb_ack ),
|
|
.i_s_wb_err ( ems_wb_err )
|
|
);
|
|
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
