| Line 93... |
Line 93... |
input mrxerr_pad_i,
|
input mrxerr_pad_i,
|
input mcoll_pad_i,
|
input mcoll_pad_i,
|
input mcrs_pad_i,
|
input mcrs_pad_i,
|
inout md_pad_io,
|
inout md_pad_io,
|
output mdc_pad_o,
|
output mdc_pad_o,
|
output phy_reset_n
|
output phy_reset_n,
|
|
|
|
output [3:0] led
|
);
|
);
|
|
|
|
|
wire sys_clk; // System clock
|
wire sys_clk; // System clock
|
wire sys_rst; // Active low reset, synchronous to sys_clk
|
wire sys_rst; // Active low reset, synchronous to sys_clk
|
| Line 329... |
Line 331... |
// T is high for tri-state output
|
// T is high for tri-state output
|
.T ( ~md_padoe_o )
|
.T ( ~md_padoe_o )
|
);
|
);
|
|
|
// Ethernet MII PHY reset
|
// Ethernet MII PHY reset
|
assign phy_reset_n = !sys_rst;
|
//assign phy_reset_n = !sys_rst;
|
|
|
// Halt core until system is ready
|
// Halt core until system is ready
|
assign system_rdy = phy_init_done && !sys_rst;
|
assign system_rdy = phy_init_done && !sys_rst;
|
|
|
// -------------------------------------------------------------
|
// -------------------------------------------------------------
|
| Line 452... |
Line 454... |
.o_wb_dat ( s_wb_dat_r[5] ),
|
.o_wb_dat ( s_wb_dat_r[5] ),
|
.i_wb_dat ( s_wb_dat_w[5] ),
|
.i_wb_dat ( s_wb_dat_w[5] ),
|
.i_wb_cyc ( s_wb_cyc [5] ),
|
.i_wb_cyc ( s_wb_cyc [5] ),
|
.i_wb_stb ( s_wb_stb [5] ),
|
.i_wb_stb ( s_wb_stb [5] ),
|
.o_wb_ack ( s_wb_ack [5] ),
|
.o_wb_ack ( s_wb_ack [5] ),
|
.o_wb_err ( s_wb_err [5] )
|
.o_wb_err ( s_wb_err [5] ),
|
|
.o_led ( led ),
|
|
.o_phy_rst_n ( phy_reset_n )
|
);
|
);
|
|
|
|
|
// -------------------------------------------------------------
|
// -------------------------------------------------------------
|
// Instantiate Timer Module
|
// Instantiate Timer Module
|
