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Line 44... |
module test_module (
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module test_module (
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input i_clk,
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input i_clk,
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output o_irq,
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output o_irq,
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output o_firq,
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output o_firq,
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output o_mem_ctrl, // 0=128MB, 1=32MB
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input [31:0] i_wb_adr,
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input [31:0] i_wb_adr,
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input [3:0] i_wb_sel,
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input [3:0] i_wb_sel,
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input i_wb_we,
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input i_wb_we,
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output [31:0] o_wb_dat,
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output [31:0] o_wb_dat,
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input [31:0] i_wb_dat,
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input [31:0] i_wb_dat,
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reg [1:0] tb_uart_status_reg = 'd0;
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reg [1:0] tb_uart_status_reg = 'd0;
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reg tb_uart_push = 'd0;
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reg tb_uart_push = 'd0;
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reg [7:0] tb_uart_txd_reg = 'd0;
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reg [7:0] tb_uart_txd_reg = 'd0;
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//synopsys translate_on
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//synopsys translate_on
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reg [1:0] sim_ctrl_reg = 'd0; // 1,2 = simulation, 0 = fpga
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reg [2:0] sim_ctrl_reg = 'd0; // 0 = fpga, other values for simulations
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reg mem_ctrl_reg = 'd0; // 0 = 128MB, 1 = 32MB main memory
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reg [31:0] test_status_reg = 'd0;
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reg [31:0] test_status_reg = 'd0;
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reg test_status_set = 'd0; // used to terminate tests
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reg test_status_set = 'd0; // used to terminate tests
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wire wb_start_write;
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wire wb_start_write;
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wire wb_start_read;
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wire wb_start_read;
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wb_start_read_d1 <= wb_start_read;
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wb_start_read_d1 <= wb_start_read;
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assign o_wb_ack = i_wb_stb && ( wb_start_write || wb_start_read_d1 );
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assign o_wb_ack = i_wb_stb && ( wb_start_write || wb_start_read_d1 );
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assign o_wb_err = 1'd0;
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assign o_wb_err = 1'd0;
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assign o_wb_dat = wb_rdata;
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assign o_wb_dat = wb_rdata;
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assign o_mem_ctrl = mem_ctrl_reg;
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// ========================================================
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// ========================================================
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// Register Reads
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// Register Reads
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// ========================================================
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// ========================================================
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always @( posedge i_clk )
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always @( posedge i_clk )
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AMBER_TEST_UART_CONTROL: wb_rdata <= {30'd0, tb_uart_control_reg};
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AMBER_TEST_UART_CONTROL: wb_rdata <= {30'd0, tb_uart_control_reg};
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AMBER_TEST_UART_STATUS: wb_rdata <= {30'd0, tb_uart_status_reg};
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AMBER_TEST_UART_STATUS: wb_rdata <= {30'd0, tb_uart_status_reg};
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AMBER_TEST_UART_TXD: wb_rdata <= {24'd0, tb_uart_txd_reg};
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AMBER_TEST_UART_TXD: wb_rdata <= {24'd0, tb_uart_txd_reg};
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//synopsys translate_on
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//synopsys translate_on
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AMBER_TEST_SIM_CTRL: wb_rdata <= {30'd0, sim_ctrl_reg};
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AMBER_TEST_SIM_CTRL: wb_rdata <= {29'd0, sim_ctrl_reg};
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AMBER_TEST_MEM_CTRL: wb_rdata <= {31'd0, mem_ctrl_reg};
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default: wb_rdata <= 32'haabbccdd;
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default: wb_rdata <= 32'haabbccdd;
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endcase
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endcase
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`endif
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`endif
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always @( posedge i_clk )
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always @( posedge i_clk )
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begin
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begin
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// Value reads as 1 in simulation, and zero in the FPGA
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// Value reads as 1 in simulation, and zero in the FPGA
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sim_ctrl_reg <= 2'd `AMBER_SIM_CTRL ;
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sim_ctrl_reg <= 3'd `AMBER_SIM_CTRL ;
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end
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end
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//synopsys translate_on
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//synopsys translate_on
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// ======================================
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// ======================================
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if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_STATUS )
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if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_STATUS )
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test_status_set <= 1'd1;
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test_status_set <= 1'd1;
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// ======================================
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// ======================================
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// Memory Configuration Register Write
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// ======================================
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always @( posedge i_clk )
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if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_MEM_CTRL )
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mem_ctrl_reg <= i_wb_dat[0];
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// ======================================
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// Test UART registers
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// Test UART registers
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// ======================================
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// ======================================
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// These control the testbench UART, not the real
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// These control the testbench UART, not the real
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// UART in system
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// UART in system
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