//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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// //
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// //
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// Timer Module //
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// Timer Module //
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// //
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// //
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// This file is part of the Amber project //
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// This file is part of the Amber project //
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// http://www.opencores.org/project,amber //
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// http://www.opencores.org/project,amber //
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// //
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// //
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// Description //
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// Description //
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// Contains 3 configurable timers. Each timer can generate //
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// Contains 3 configurable timers. Each timer can generate //
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// either one-shot or cyclical interrupts //
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// either one-shot or cyclical interrupts //
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// //
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// //
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// Author(s): //
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// Author(s): //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// //
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// //
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//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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// //
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// //
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// Copyright (C) 2010 Authors and OPENCORES.ORG //
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// Copyright (C) 2010 Authors and OPENCORES.ORG //
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// //
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// //
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// This source file may be used and distributed without //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// the original copyright notice and the associated disclaimer. //
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// //
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// //
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// This source file is free software; you can redistribute it //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// later version. //
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// //
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// //
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// This source is distributed in the hope that it will be //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// details. //
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// //
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// //
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// You should have received a copy of the GNU Lesser General //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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// //
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//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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`include "global_defines.v"
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|
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module timer_module #(
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module timer_module #(
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parameter WB_DWIDTH = 32,
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parameter WB_DWIDTH = 32,
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parameter WB_SWIDTH = 4
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parameter WB_SWIDTH = 4
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)(
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)(
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input i_clk,
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input i_clk,
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input [31:0] i_wb_adr,
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input [31:0] i_wb_adr,
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input [WB_SWIDTH-1:0] i_wb_sel,
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input [WB_SWIDTH-1:0] i_wb_sel,
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input i_wb_we,
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input i_wb_we,
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output [WB_DWIDTH-1:0] o_wb_dat,
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output [WB_DWIDTH-1:0] o_wb_dat,
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input [WB_DWIDTH-1:0] i_wb_dat,
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input [WB_DWIDTH-1:0] i_wb_dat,
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input i_wb_cyc,
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input i_wb_cyc,
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input i_wb_stb,
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input i_wb_stb,
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output o_wb_ack,
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output o_wb_ack,
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output o_wb_err,
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output o_wb_err,
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output [2:0] o_timer_int
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output [2:0] o_timer_int
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|
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);
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);
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`include "register_addresses.v"
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`include "register_addresses.v"
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// Wishbone registers
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// Wishbone registers
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reg [15:0] timer0_load_reg = 'd0; // initial count value
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reg [15:0] timer0_load_reg = 'd0; // initial count value
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reg [15:0] timer1_load_reg = 'd0; // initial count value
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reg [15:0] timer1_load_reg = 'd0; // initial count value
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reg [15:0] timer2_load_reg = 'd0; // initial count value
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reg [15:0] timer2_load_reg = 'd0; // initial count value
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reg [23:0] timer0_value_reg = 24'hffffff; // current count value
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reg [23:0] timer0_value_reg = 24'hffffff; // current count value
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reg [23:0] timer1_value_reg = 24'hffffff; // current count value
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reg [23:0] timer1_value_reg = 24'hffffff; // current count value
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reg [23:0] timer2_value_reg = 24'hffffff; // current count value
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reg [23:0] timer2_value_reg = 24'hffffff; // current count value
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reg [7:0] timer0_ctrl_reg = 'd0; // control bits
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reg [7:0] timer0_ctrl_reg = 'd0; // control bits
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reg [7:0] timer1_ctrl_reg = 'd0; // control bits
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reg [7:0] timer1_ctrl_reg = 'd0; // control bits
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reg [7:0] timer2_ctrl_reg = 'd0; // control bits
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reg [7:0] timer2_ctrl_reg = 'd0; // control bits
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reg timer0_int_reg = 'd0; // interrupt flag
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reg timer0_int_reg = 'd0; // interrupt flag
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reg timer1_int_reg = 'd0; // interrupt flag
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reg timer1_int_reg = 'd0; // interrupt flag
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reg timer2_int_reg = 'd0; // interrupt flag
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reg timer2_int_reg = 'd0; // interrupt flag
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// Wishbone interface
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// Wishbone interface
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reg [31:0] wb_rdata32 = 'd0;
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reg [31:0] wb_rdata32 = 'd0;
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wire wb_start_write;
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wire wb_start_write;
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wire wb_start_read;
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wire wb_start_read;
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reg wb_start_read_d1 = 'd0;
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reg wb_start_read_d1 = 'd0;
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wire [31:0] wb_wdata32;
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wire [31:0] wb_wdata32;
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// ======================================================
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// ======================================================
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// Wishbone Interface
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// Wishbone Interface
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// ======================================================
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// ======================================================
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// Can't start a write while a read is completing. The ack for the read cycle
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// Can't start a write while a read is completing. The ack for the read cycle
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// needs to be sent first
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// needs to be sent first
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assign wb_start_write = i_wb_stb && i_wb_we && !wb_start_read_d1;
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assign wb_start_write = i_wb_stb && i_wb_we && !wb_start_read_d1;
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assign wb_start_read = i_wb_stb && !i_wb_we && !o_wb_ack;
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assign wb_start_read = i_wb_stb && !i_wb_we && !o_wb_ack;
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always @( posedge i_clk )
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always @( posedge i_clk )
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wb_start_read_d1 <= wb_start_read;
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wb_start_read_d1 <= wb_start_read;
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assign o_wb_err = 1'd0;
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assign o_wb_err = 1'd0;
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assign o_wb_ack = i_wb_stb && ( wb_start_write || wb_start_read_d1 );
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assign o_wb_ack = i_wb_stb && ( wb_start_write || wb_start_read_d1 );
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generate
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generate
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if (WB_DWIDTH == 128)
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if (WB_DWIDTH == 128)
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begin : wb128
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begin : wb128
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assign wb_wdata32 = i_wb_adr[3:2] == 2'd3 ? i_wb_dat[127:96] :
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assign wb_wdata32 = i_wb_adr[3:2] == 2'd3 ? i_wb_dat[127:96] :
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i_wb_adr[3:2] == 2'd2 ? i_wb_dat[ 95:64] :
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i_wb_adr[3:2] == 2'd2 ? i_wb_dat[ 95:64] :
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i_wb_adr[3:2] == 2'd1 ? i_wb_dat[ 63:32] :
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i_wb_adr[3:2] == 2'd1 ? i_wb_dat[ 63:32] :
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i_wb_dat[ 31: 0] ;
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i_wb_dat[ 31: 0] ;
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assign o_wb_dat = {4{wb_rdata32}};
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assign o_wb_dat = {4{wb_rdata32}};
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end
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end
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else
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else
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begin : wb32
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begin : wb32
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assign wb_wdata32 = i_wb_dat;
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assign wb_wdata32 = i_wb_dat;
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assign o_wb_dat = wb_rdata32;
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assign o_wb_dat = wb_rdata32;
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end
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end
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endgenerate
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endgenerate
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// ========================================================
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// ========================================================
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// Timer Interrupt Outputs
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// Timer Interrupt Outputs
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// ========================================================
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// ========================================================
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assign o_timer_int = { timer2_int_reg,
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assign o_timer_int = { timer2_int_reg,
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timer1_int_reg,
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timer1_int_reg,
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timer0_int_reg };
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timer0_int_reg };
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// ========================================================
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// ========================================================
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// Register Writes
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// Register Writes
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// ========================================================
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// ========================================================
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always @( posedge i_clk )
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always @( posedge i_clk )
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begin
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begin
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if ( wb_start_write )
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if ( wb_start_write )
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case ( i_wb_adr[15:0] )
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case ( i_wb_adr[15:0] )
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// write to timer control registers
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// write to timer control registers
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AMBER_TM_TIMER0_CTRL: timer0_ctrl_reg <= i_wb_dat[7:0];
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AMBER_TM_TIMER0_CTRL: timer0_ctrl_reg <= i_wb_dat[7:0];
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AMBER_TM_TIMER1_CTRL: timer1_ctrl_reg <= i_wb_dat[7:0];
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AMBER_TM_TIMER1_CTRL: timer1_ctrl_reg <= i_wb_dat[7:0];
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AMBER_TM_TIMER2_CTRL: timer2_ctrl_reg <= i_wb_dat[7:0];
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AMBER_TM_TIMER2_CTRL: timer2_ctrl_reg <= i_wb_dat[7:0];
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endcase
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endcase
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// -------------------------------
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// -------------------------------
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// Timer 0
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// Timer 0
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// -------------------------------
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// -------------------------------
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if ( wb_start_write && i_wb_adr[15:0] == AMBER_TM_TIMER0_LOAD )
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if ( wb_start_write && i_wb_adr[15:0] == AMBER_TM_TIMER0_LOAD )
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begin
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begin
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timer0_value_reg <= {i_wb_dat[15:0], 8'd0};
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timer0_value_reg <= {i_wb_dat[15:0], 8'd0};
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timer0_load_reg <= i_wb_dat[15:0];
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timer0_load_reg <= i_wb_dat[15:0];
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end
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end
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else if ( timer0_ctrl_reg[7] ) // Timer Enabled
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else if ( timer0_ctrl_reg[7] ) // Timer Enabled
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begin
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begin
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if ( timer0_value_reg == 24'd0 )
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if ( timer0_value_reg == 24'd0 )
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begin
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begin
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if ( timer0_ctrl_reg[6] ) // periodic
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if ( timer0_ctrl_reg[6] ) // periodic
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timer0_value_reg <= {timer0_load_reg, 8'd0};
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timer0_value_reg <= {timer0_load_reg, 8'd0};
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else
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else
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timer0_value_reg <= 24'hffffff;
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timer0_value_reg <= 24'hffffff;
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end
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end
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else
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else
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case ( timer0_ctrl_reg[3:2] )
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case ( timer0_ctrl_reg[3:2] )
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2'b00: timer0_value_reg <= (timer0_value_reg & 24'hffff00) - 9'd256;
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2'b00: timer0_value_reg <= (timer0_value_reg & 24'hffff00) - 9'd256;
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2'b01: timer0_value_reg <= (timer0_value_reg & 24'hfffff0) - 9'd16;
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2'b01: timer0_value_reg <= (timer0_value_reg & 24'hfffff0) - 9'd16;
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2'b10: timer0_value_reg <= timer0_value_reg - 1'd1;
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2'b10: timer0_value_reg <= timer0_value_reg - 1'd1;
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default:
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default:
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begin
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begin
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//synopsys translate_off
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//synopsys translate_off
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`TB_ERROR_MESSAGE
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`TB_ERROR_MESSAGE
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$write("unknown Timer Module Prescale Value %d for Timer 0",
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$write("unknown Timer Module Prescale Value %d for Timer 0",
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timer0_ctrl_reg[3:2]);
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timer0_ctrl_reg[3:2]);
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//synopsys translate_on
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//synopsys translate_on
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end
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end
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endcase
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endcase
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end
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end
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// -------------------------------
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// -------------------------------
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// Timer 1
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// Timer 1
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// -------------------------------
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// -------------------------------
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if ( wb_start_write && i_wb_adr[15:0] == AMBER_TM_TIMER1_LOAD )
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if ( wb_start_write && i_wb_adr[15:0] == AMBER_TM_TIMER1_LOAD )
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begin
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begin
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timer1_value_reg <= {i_wb_dat[15:0], 8'd0};
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timer1_value_reg <= {i_wb_dat[15:0], 8'd0};
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timer1_load_reg <= i_wb_dat[15:0];
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timer1_load_reg <= i_wb_dat[15:0];
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end
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end
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else if ( timer1_ctrl_reg[7] ) // Timer Enabled
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else if ( timer1_ctrl_reg[7] ) // Timer Enabled
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begin
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begin
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if ( timer1_value_reg == 24'd0 )
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if ( timer1_value_reg == 24'd0 )
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begin
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begin
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if ( timer1_ctrl_reg[6] ) // periodic
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if ( timer1_ctrl_reg[6] ) // periodic
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timer1_value_reg <= {timer1_load_reg, 8'd0};
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timer1_value_reg <= {timer1_load_reg, 8'd0};
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else
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else
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timer1_value_reg <= 24'hffffff;
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timer1_value_reg <= 24'hffffff;
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end
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end
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else
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else
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case ( timer1_ctrl_reg[3:2] )
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case ( timer1_ctrl_reg[3:2] )
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2'b00: timer1_value_reg <= (timer1_value_reg & 24'hffff00) - 9'd256;
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2'b00: timer1_value_reg <= (timer1_value_reg & 24'hffff00) - 9'd256;
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2'b01: timer1_value_reg <= (timer1_value_reg & 24'hfffff0) - 9'd16;
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2'b01: timer1_value_reg <= (timer1_value_reg & 24'hfffff0) - 9'd16;
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2'b10: timer1_value_reg <= timer1_value_reg - 1'd1;
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2'b10: timer1_value_reg <= timer1_value_reg - 1'd1;
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default:
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default:
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begin
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begin
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//synopsys translate_off
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//synopsys translate_off
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`TB_ERROR_MESSAGE
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`TB_ERROR_MESSAGE
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$write("unknown Timer Module Prescale Value %d for Timer 1",
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$write("unknown Timer Module Prescale Value %d for Timer 1",
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timer1_ctrl_reg[3:2]);
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timer1_ctrl_reg[3:2]);
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//synopsys translate_on
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//synopsys translate_on
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end
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end
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endcase
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endcase
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end
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end
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// -------------------------------
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// -------------------------------
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// Timer 2
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// Timer 2
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// -------------------------------
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// -------------------------------
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if ( wb_start_write && i_wb_adr[15:0] == AMBER_TM_TIMER2_LOAD )
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if ( wb_start_write && i_wb_adr[15:0] == AMBER_TM_TIMER2_LOAD )
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begin
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begin
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timer2_value_reg <= {i_wb_dat[15:0], 8'd0};
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timer2_value_reg <= {i_wb_dat[15:0], 8'd0};
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timer2_load_reg <= i_wb_dat[15:0];
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timer2_load_reg <= i_wb_dat[15:0];
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end
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end
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else if ( timer2_ctrl_reg[7] ) // Timer Enabled
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else if ( timer2_ctrl_reg[7] ) // Timer Enabled
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begin
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begin
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if ( timer2_value_reg == 24'd0 )
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if ( timer2_value_reg == 24'd0 )
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begin
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begin
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if ( timer2_ctrl_reg[6] ) // periodic
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if ( timer2_ctrl_reg[6] ) // periodic
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timer2_value_reg <= {timer2_load_reg, 8'd0};
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timer2_value_reg <= {timer2_load_reg, 8'd0};
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else
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else
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timer2_value_reg <= 24'hffffff;
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timer2_value_reg <= 24'hffffff;
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end
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end
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else
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else
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case ( timer2_ctrl_reg[3:2] )
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case ( timer2_ctrl_reg[3:2] )
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2'b00: timer2_value_reg <= (timer2_value_reg & 24'hffff00) - 9'd256;
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2'b00: timer2_value_reg <= (timer2_value_reg & 24'hffff00) - 9'd256;
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2'b01: timer2_value_reg <= (timer2_value_reg & 24'hfffff0) - 9'd16;
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2'b01: timer2_value_reg <= (timer2_value_reg & 24'hfffff0) - 9'd16;
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2'b10: timer2_value_reg <= timer2_value_reg - 1'd1;
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2'b10: timer2_value_reg <= timer2_value_reg - 1'd1;
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default:
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default:
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begin
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begin
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//synopsys translate_off
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//synopsys translate_off
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`TB_ERROR_MESSAGE
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`TB_ERROR_MESSAGE
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$write("unknown Timer Module Prescale Value %d for Timer 2",
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$write("unknown Timer Module Prescale Value %d for Timer 2",
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timer2_ctrl_reg[3:2]);
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timer2_ctrl_reg[3:2]);
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//synopsys translate_on
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//synopsys translate_on
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end
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end
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endcase
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endcase
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end
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end
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|
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// -------------------------------
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// -------------------------------
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// Timer generated Interrupt Flags
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// Timer generated Interrupt Flags
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// -------------------------------
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// -------------------------------
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if ( wb_start_write && i_wb_adr[15:0] == AMBER_TM_TIMER0_CLR )
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if ( wb_start_write && i_wb_adr[15:0] == AMBER_TM_TIMER0_CLR )
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timer0_int_reg <= 1'd0;
|
timer0_int_reg <= 1'd0;
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else if ( timer0_value_reg == 24'd0 )
|
else if ( timer0_value_reg == 24'd0 )
|
// stays asserted until cleared
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// stays asserted until cleared
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timer0_int_reg <= 1'd1;
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timer0_int_reg <= 1'd1;
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|
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if ( wb_start_write && i_wb_adr[15:0] == AMBER_TM_TIMER1_CLR)
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if ( wb_start_write && i_wb_adr[15:0] == AMBER_TM_TIMER1_CLR)
|
timer1_int_reg <= 1'd0;
|
timer1_int_reg <= 1'd0;
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else if ( timer1_value_reg == 24'd0 )
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else if ( timer1_value_reg == 24'd0 )
|
// stays asserted until cleared
|
// stays asserted until cleared
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timer1_int_reg <= 1'd1;
|
timer1_int_reg <= 1'd1;
|
|
|
if ( wb_start_write && i_wb_adr[15:0] == AMBER_TM_TIMER2_CLR)
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if ( wb_start_write && i_wb_adr[15:0] == AMBER_TM_TIMER2_CLR)
|
timer2_int_reg <= 1'd0;
|
timer2_int_reg <= 1'd0;
|
else if ( timer2_value_reg == 24'd0 )
|
else if ( timer2_value_reg == 24'd0 )
|
// stays asserted until cleared
|
// stays asserted until cleared
|
timer2_int_reg <= 1'd1;
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timer2_int_reg <= 1'd1;
|
|
|
end
|
end
|
|
|
|
|
// ========================================================
|
// ========================================================
|
// Register Reads
|
// Register Reads
|
// ========================================================
|
// ========================================================
|
always @( posedge i_clk )
|
always @( posedge i_clk )
|
if ( wb_start_read )
|
if ( wb_start_read )
|
case ( i_wb_adr[15:0] )
|
case ( i_wb_adr[15:0] )
|
AMBER_TM_TIMER0_LOAD: wb_rdata32 <= {16'd0, timer0_load_reg};
|
AMBER_TM_TIMER0_LOAD: wb_rdata32 <= {16'd0, timer0_load_reg};
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AMBER_TM_TIMER1_LOAD: wb_rdata32 <= {16'd0, timer1_load_reg};
|
AMBER_TM_TIMER1_LOAD: wb_rdata32 <= {16'd0, timer1_load_reg};
|
AMBER_TM_TIMER2_LOAD: wb_rdata32 <= {16'd0, timer2_load_reg};
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AMBER_TM_TIMER2_LOAD: wb_rdata32 <= {16'd0, timer2_load_reg};
|
AMBER_TM_TIMER0_CTRL: wb_rdata32 <= {24'd0,
|
AMBER_TM_TIMER0_CTRL: wb_rdata32 <= {24'd0,
|
timer0_ctrl_reg[7:6],
|
timer0_ctrl_reg[7:6],
|
2'd0,
|
2'd0,
|
timer0_ctrl_reg[3:2],
|
timer0_ctrl_reg[3:2],
|
2'd0
|
2'd0
|
};
|
};
|
AMBER_TM_TIMER1_CTRL: wb_rdata32 <= {24'd0,
|
AMBER_TM_TIMER1_CTRL: wb_rdata32 <= {24'd0,
|
timer1_ctrl_reg[7:6],
|
timer1_ctrl_reg[7:6],
|
2'd0,
|
2'd0,
|
timer1_ctrl_reg[3:2],
|
timer1_ctrl_reg[3:2],
|
2'd0
|
2'd0
|
};
|
};
|
AMBER_TM_TIMER2_CTRL: wb_rdata32 <= {24'd0,
|
AMBER_TM_TIMER2_CTRL: wb_rdata32 <= {24'd0,
|
timer2_ctrl_reg[7:6],
|
timer2_ctrl_reg[7:6],
|
2'd0,
|
2'd0,
|
timer2_ctrl_reg[3:2],
|
timer2_ctrl_reg[3:2],
|
2'd0
|
2'd0
|
};
|
};
|
AMBER_TM_TIMER0_VALUE: wb_rdata32 <= {16'd0, timer0_value_reg[23:8]};
|
AMBER_TM_TIMER0_VALUE: wb_rdata32 <= {16'd0, timer0_value_reg[23:8]};
|
AMBER_TM_TIMER1_VALUE: wb_rdata32 <= {16'd0, timer1_value_reg[23:8]};
|
AMBER_TM_TIMER1_VALUE: wb_rdata32 <= {16'd0, timer1_value_reg[23:8]};
|
AMBER_TM_TIMER2_VALUE: wb_rdata32 <= {16'd0, timer2_value_reg[23:8]};
|
AMBER_TM_TIMER2_VALUE: wb_rdata32 <= {16'd0, timer2_value_reg[23:8]};
|
|
|
default: wb_rdata32 <= 32'h66778899;
|
default: wb_rdata32 <= 32'h66778899;
|
|
|
endcase
|
endcase
|
|
|
|
|
|
|
// =======================================================================================
|
// =======================================================================================
|
// =======================================================================================
|
// =======================================================================================
|
// =======================================================================================
|
// =======================================================================================
|
// Non-synthesizable debug code
|
// Non-synthesizable debug code
|
// =======================================================================================
|
// =======================================================================================
|
|
|
|
|
//synopsys translate_off
|
//synopsys translate_off
|
|
|
`ifdef AMBER_CT_DEBUG
|
`ifdef AMBER_CT_DEBUG
|
|
|
reg timer0_int_reg_d1;
|
reg timer0_int_reg_d1;
|
reg timer1_int_reg_d1;
|
reg timer1_int_reg_d1;
|
reg timer2_int_reg_d1;
|
reg timer2_int_reg_d1;
|
wire wb_read_ack = i_wb_stb && !i_wb_we && o_wb_ack;
|
wire wb_read_ack = i_wb_stb && !i_wb_we && o_wb_ack;
|
|
|
// -----------------------------------------------
|
// -----------------------------------------------
|
// Report Timer Module Register accesses
|
// Report Timer Module Register accesses
|
// -----------------------------------------------
|
// -----------------------------------------------
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ( wb_read_ack || wb_start_write )
|
if ( wb_read_ack || wb_start_write )
|
begin
|
begin
|
`TB_DEBUG_MESSAGE
|
`TB_DEBUG_MESSAGE
|
|
|
if ( wb_start_write )
|
if ( wb_start_write )
|
$write("Write 0x%08x to ", i_wb_dat);
|
$write("Write 0x%08x to ", i_wb_dat);
|
else
|
else
|
$write("Read 0x%08x from ", o_wb_dat);
|
$write("Read 0x%08x from ", o_wb_dat);
|
|
|
case ( i_wb_adr[15:0] )
|
case ( i_wb_adr[15:0] )
|
AMBER_TM_TIMER0_LOAD:
|
AMBER_TM_TIMER0_LOAD:
|
$write(" Timer Module Timer 0 Load");
|
$write(" Timer Module Timer 0 Load");
|
AMBER_TM_TIMER1_LOAD:
|
AMBER_TM_TIMER1_LOAD:
|
$write(" Timer Module Timer 1 Load");
|
$write(" Timer Module Timer 1 Load");
|
AMBER_TM_TIMER2_LOAD:
|
AMBER_TM_TIMER2_LOAD:
|
$write(" Timer Module Timer 2 Load");
|
$write(" Timer Module Timer 2 Load");
|
AMBER_TM_TIMER0_CTRL:
|
AMBER_TM_TIMER0_CTRL:
|
$write(" Timer Module Timer 0 Control");
|
$write(" Timer Module Timer 0 Control");
|
AMBER_TM_TIMER1_CTRL:
|
AMBER_TM_TIMER1_CTRL:
|
$write(" Timer Module Timer 1 Control");
|
$write(" Timer Module Timer 1 Control");
|
AMBER_TM_TIMER2_CTRL:
|
AMBER_TM_TIMER2_CTRL:
|
$write(" Timer Module Timer 2 Control");
|
$write(" Timer Module Timer 2 Control");
|
AMBER_TM_TIMER0_VALUE:
|
AMBER_TM_TIMER0_VALUE:
|
$write(" Timer Module Timer 0 Value");
|
$write(" Timer Module Timer 0 Value");
|
AMBER_TM_TIMER1_VALUE:
|
AMBER_TM_TIMER1_VALUE:
|
$write(" Timer Module Timer 1 Value");
|
$write(" Timer Module Timer 1 Value");
|
AMBER_TM_TIMER2_VALUE:
|
AMBER_TM_TIMER2_VALUE:
|
$write(" Timer Module Timer 2 Value");
|
$write(" Timer Module Timer 2 Value");
|
AMBER_TM_TIMER0_CLR:
|
AMBER_TM_TIMER0_CLR:
|
$write(" Timer Module Timer 0 Clear");
|
$write(" Timer Module Timer 0 Clear");
|
AMBER_TM_TIMER1_CLR:
|
AMBER_TM_TIMER1_CLR:
|
$write(" Timer Module Timer 1 Clear");
|
$write(" Timer Module Timer 1 Clear");
|
AMBER_TM_TIMER2_CLR:
|
AMBER_TM_TIMER2_CLR:
|
$write(" Timer Module Timer 2 Clear");
|
$write(" Timer Module Timer 2 Clear");
|
|
|
default:
|
default:
|
begin
|
begin
|
$write(" unknown Amber IC Register region");
|
$write(" unknown Amber IC Register region");
|
$write(", Address 0x%08h\n", i_wb_adr);
|
$write(", Address 0x%08h\n", i_wb_adr);
|
`TB_ERROR_MESSAGE
|
`TB_ERROR_MESSAGE
|
end
|
end
|
endcase
|
endcase
|
|
|
$write(", Address 0x%08h\n", i_wb_adr);
|
$write(", Address 0x%08h\n", i_wb_adr);
|
end
|
end
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
timer0_int_reg_d1 <= timer0_int_reg;
|
timer0_int_reg_d1 <= timer0_int_reg;
|
timer1_int_reg_d1 <= timer1_int_reg;
|
timer1_int_reg_d1 <= timer1_int_reg;
|
timer2_int_reg_d1 <= timer2_int_reg;
|
timer2_int_reg_d1 <= timer2_int_reg;
|
|
|
if ( timer0_int_reg && !timer0_int_reg_d1 )
|
if ( timer0_int_reg && !timer0_int_reg_d1 )
|
begin
|
begin
|
`TB_DEBUG_MESSAGE
|
`TB_DEBUG_MESSAGE
|
$display("Timer Module Timer 0 Interrupt");
|
$display("Timer Module Timer 0 Interrupt");
|
end
|
end
|
if ( timer1_int_reg && !timer1_int_reg_d1 )
|
if ( timer1_int_reg && !timer1_int_reg_d1 )
|
begin
|
begin
|
`TB_DEBUG_MESSAGE
|
`TB_DEBUG_MESSAGE
|
$display("Timer Module Timer 1 Interrupt");
|
$display("Timer Module Timer 1 Interrupt");
|
end
|
end
|
if ( timer2_int_reg && !timer2_int_reg_d1 )
|
if ( timer2_int_reg && !timer2_int_reg_d1 )
|
begin
|
begin
|
`TB_DEBUG_MESSAGE
|
`TB_DEBUG_MESSAGE
|
$display("Timer Module Timer 2 Interrupt");
|
$display("Timer Module Timer 2 Interrupt");
|
end
|
end
|
end
|
end
|
|
|
`endif
|
`endif
|
|
|
//synopsys translate_on
|
//synopsys translate_on
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|
