//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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// //
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// //
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// UART //
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// UART //
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// //
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// //
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// This file is part of the Amber project //
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// This file is part of the Amber project //
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// http://www.opencores.org/project,amber //
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// http://www.opencores.org/project,amber //
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// //
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// //
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// Description //
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// Description //
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// This is a synchronous UART meaning it uses the system //
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// This is a synchronous UART meaning it uses the system //
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// clock rather than having its own clock. This means the //
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// clock rather than having its own clock. This means the //
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// standard UART Baud rates are approximated and not exact. //
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// standard UART Baud rates are approximated and not exact. //
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// However the UART tandard provides for a 10% margin on //
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// However the UART tandard provides for a 10% margin on //
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// baud rates and this module is much more accurate than that. //
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// baud rates and this module is much more accurate than that. //
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// //
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// //
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// The Baud rate must be set before synthesis and is not //
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// The Baud rate must be set before synthesis and is not //
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// programmable. This keeps the UART small. //
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// programmable. This keeps the UART small. //
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// //
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// //
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// The UART uses 8 data bits, 1 stop bit and no parity bits. //
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// The UART uses 8 data bits, 1 stop bit and no parity bits. //
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// //
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// //
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// The UART has a 16-byte transmit and a 16-byte receive FIFO //
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// The UART has a 16-byte transmit and a 16-byte receive FIFO //
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// These FIFOs are implemented in flipflops - FPGAs have lots //
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// These FIFOs are implemented in flipflops - FPGAs have lots //
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// of flipflops! //
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// of flipflops! //
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// //
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// //
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// Author(s): //
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// Author(s): //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// //
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// //
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//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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// //
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// //
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// Copyright (C) 2010 Authors and OPENCORES.ORG //
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// Copyright (C) 2010 Authors and OPENCORES.ORG //
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// //
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// //
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// This source file may be used and distributed without //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// the original copyright notice and the associated disclaimer. //
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// //
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// //
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// This source file is free software; you can redistribute it //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// later version. //
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// //
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// //
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// This source is distributed in the hope that it will be //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// details. //
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// //
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// //
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// You should have received a copy of the GNU Lesser General //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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// //
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//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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`include "system_config_defines.v"
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`include "system_config_defines.v"
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// Normally AMBER_UART_BAUD is defined in the system_config_defines.v file.
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`ifndef AMBER_UART_BAUD
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`define AMBER_UART_BAUD 230400
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`endif
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module uart (
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module uart (
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input i_clk,
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input i_clk,
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input [31:0] i_wb_adr,
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input [31:0] i_wb_adr,
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input [3:0] i_wb_sel,
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input [3:0] i_wb_sel,
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input i_wb_we,
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input i_wb_we,
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output [31:0] o_wb_dat,
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output [31:0] o_wb_dat,
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input [31:0] i_wb_dat,
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input [31:0] i_wb_dat,
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input i_wb_cyc,
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input i_wb_cyc,
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input i_wb_stb,
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input i_wb_stb,
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output o_wb_ack,
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output o_wb_ack,
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output o_wb_err,
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output o_wb_err,
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|
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output o_uart_int,
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output o_uart_int,
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input i_uart_cts_n, // Clear To Send
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input i_uart_cts_n, // Clear To Send
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output o_uart_txd, // Transmit data
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output o_uart_txd, // Transmit data
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output o_uart_rts_n, // Request to Send
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output o_uart_rts_n, // Request to Send
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input i_uart_rxd // Receive data
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input i_uart_rxd // Receive data
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|
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);
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);
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`include "register_addresses.v"
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`include "register_addresses.v"
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localparam [3:0] TXD_IDLE = 4'd0,
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localparam [3:0] TXD_IDLE = 4'd0,
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TXD_START = 4'd1,
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TXD_START = 4'd1,
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TXD_DATA0 = 4'd2,
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TXD_DATA0 = 4'd2,
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TXD_DATA1 = 4'd3,
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TXD_DATA1 = 4'd3,
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TXD_DATA2 = 4'd4,
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TXD_DATA2 = 4'd4,
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TXD_DATA3 = 4'd5,
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TXD_DATA3 = 4'd5,
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TXD_DATA4 = 4'd6,
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TXD_DATA4 = 4'd6,
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TXD_DATA5 = 4'd7,
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TXD_DATA5 = 4'd7,
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TXD_DATA6 = 4'd8,
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TXD_DATA6 = 4'd8,
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TXD_DATA7 = 4'd9,
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TXD_DATA7 = 4'd9,
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TXD_STOP1 = 4'd10,
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TXD_STOP1 = 4'd10,
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TXD_STOP2 = 4'd11,
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TXD_STOP2 = 4'd11,
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TXD_STOP3 = 4'd12;
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TXD_STOP3 = 4'd12;
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localparam [3:0] RXD_IDLE = 4'd0,
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localparam [3:0] RXD_IDLE = 4'd0,
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RXD_START = 4'd1,
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RXD_START = 4'd1,
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RXD_START_MID = 4'd2,
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RXD_START_MID = 4'd2,
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RXD_DATA0 = 4'd3,
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RXD_START_MID1 = 4'd3,
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RXD_DATA1 = 4'd4,
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RXD_DATA0 = 4'd4,
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RXD_DATA2 = 4'd5,
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RXD_DATA1 = 4'd5,
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RXD_DATA3 = 4'd6,
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RXD_DATA2 = 4'd6,
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RXD_DATA4 = 4'd7,
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RXD_DATA3 = 4'd7,
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RXD_DATA5 = 4'd8,
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RXD_DATA4 = 4'd8,
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RXD_DATA6 = 4'd9,
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RXD_DATA5 = 4'd9,
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RXD_DATA7 = 4'd10,
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RXD_DATA6 = 4'd10,
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RXD_STOP = 4'd11;
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RXD_DATA7 = 4'd11,
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RXD_STOP = 4'd12;
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localparam RX_INTERRUPT_COUNT = 24'h3fffff;
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localparam RX_INTERRUPT_COUNT = 24'h3fffff;
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// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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// Baud Rate Configuration
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// Baud Rate Configuration
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// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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`ifndef Veritak
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`ifndef Veritak
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localparam real UART_BAUD = `AMBER_UART_BAUD; // Hz
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localparam real UART_BAUD = `AMBER_UART_BAUD; // Hz
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`ifdef XILINX_VIRTEX6_FPGA
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localparam real CLK_FREQ = 1000.0 / `AMBER_CLK_DIVIDER ; // MHz
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`else
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localparam real CLK_FREQ = 800.0 / `AMBER_CLK_DIVIDER ; // MHz
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localparam real CLK_FREQ = 800.0 / `AMBER_CLK_DIVIDER ; // MHz
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`endif
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localparam real UART_BIT_PERIOD = 1000000000 / UART_BAUD; // nS
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localparam real UART_BIT_PERIOD = 1000000000 / UART_BAUD; // nS
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localparam real UART_WORD_PERIOD = ( UART_BIT_PERIOD * 12 ); // nS
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localparam real UART_WORD_PERIOD = ( UART_BIT_PERIOD * 12 ); // nS
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localparam real CLK_PERIOD = 1000 / CLK_FREQ; // nS
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localparam real CLK_PERIOD = 1000 / CLK_FREQ; // nS
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localparam real CLKS_PER_WORD = UART_WORD_PERIOD / CLK_PERIOD;
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localparam real CLKS_PER_WORD = UART_WORD_PERIOD / CLK_PERIOD;
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localparam real CLKS_PER_BIT = CLKS_PER_WORD / 12;
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localparam real CLKS_PER_BIT = CLKS_PER_WORD / 12;
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// These are rounded to the nearest whole number
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// These are rounded to the nearest whole number
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// i.e. 29.485960 -> 29
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// i.e. 29.485960 -> 29
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// 29.566303 -> 30
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// 29.566303 -> 30
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localparam [9:0] TX_BITPULSE_COUNT = CLKS_PER_BIT;
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localparam [9:0] TX_BITPULSE_COUNT = CLKS_PER_BIT;
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localparam [9:0] TX_CLKS_PER_WORD = CLKS_PER_WORD;
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localparam [9:0] TX_CLKS_PER_WORD = CLKS_PER_WORD;
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`else
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`else
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localparam [9:0] TX_BITPULSE_COUNT = 30;
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localparam [9:0] TX_BITPULSE_COUNT = 30;
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localparam [9:0] TX_CLKS_PER_WORD = 360;
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localparam [9:0] TX_CLKS_PER_WORD = 360;
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`endif
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`endif
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localparam [9:0] TX_BITADJUST_COUNT = TX_CLKS_PER_WORD - 11*TX_BITPULSE_COUNT;
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localparam [9:0] TX_BITADJUST_COUNT = TX_CLKS_PER_WORD - 11*TX_BITPULSE_COUNT;
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localparam [9:0] RX_BITPULSE_COUNT = TX_BITPULSE_COUNT-2;
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localparam [9:0] RX_BITPULSE_COUNT = TX_BITPULSE_COUNT-2;
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localparam [9:0] RX_HALFPULSE_COUNT = TX_BITPULSE_COUNT/2 - 4;
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localparam [9:0] RX_HALFPULSE_COUNT = TX_BITPULSE_COUNT/2 - 4;
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// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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reg tx_interrupt = 'd0;
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reg tx_interrupt = 'd0;
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reg rx_interrupt = 'd0;
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reg rx_interrupt = 'd0;
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reg [23:0] rx_int_timer = 'd0;
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reg [23:0] rx_int_timer = 'd0;
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wire fifo_enable;
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wire fifo_enable;
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reg [7:0] tx_fifo [0:15];
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reg [7:0] tx_fifo [0:15];
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wire tx_fifo_full;
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wire tx_fifo_full;
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wire tx_fifo_empty;
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wire tx_fifo_empty;
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wire tx_fifo_half_or_less_full;
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wire tx_fifo_half_or_less_full;
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wire tx_fifo_push;
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wire tx_fifo_push;
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wire tx_fifo_push_not_full;
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wire tx_fifo_push_not_full;
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wire tx_fifo_pop_not_empty;
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wire tx_fifo_pop_not_empty;
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reg [4:0] tx_fifo_wp = 'd0;
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reg [4:0] tx_fifo_wp = 'd0;
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reg [4:0] tx_fifo_rp = 'd0;
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reg [4:0] tx_fifo_rp = 'd0;
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reg [4:0] tx_fifo_count = 'd0; // number of entries in the fifo
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reg [4:0] tx_fifo_count = 'd0; // number of entries in the fifo
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reg tx_fifo_full_flag = 'd0;
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reg tx_fifo_full_flag = 'd0;
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reg [7:0] rx_fifo [0:15];
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reg [7:0] rx_fifo [0:15];
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reg rx_fifo_empty = 1'd1;
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reg rx_fifo_empty = 1'd1;
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reg rx_fifo_full = 1'd0;
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reg rx_fifo_full = 1'd0;
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wire rx_fifo_half_or_more; // true when half full or greater
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wire rx_fifo_half_or_more; // true when half full or greater
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reg [4:0] rx_fifo_count = 'd0; // number of entries in the fifo
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reg [4:0] rx_fifo_count = 'd0; // number of entries in the fifo
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wire rx_fifo_push;
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wire rx_fifo_push;
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wire rx_fifo_push_not_full;
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wire rx_fifo_push_not_full;
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wire rx_fifo_pop;
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wire rx_fifo_pop;
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wire rx_fifo_pop_not_empty;
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wire rx_fifo_pop_not_empty;
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reg [4:0] rx_fifo_wp = 'd0;
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reg [4:0] rx_fifo_wp = 'd0;
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reg [4:0] rx_fifo_rp = 'd0;
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reg [4:0] rx_fifo_rp = 'd0;
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wire [7:0] tx_byte;
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wire [7:0] tx_byte;
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reg [3:0] txd_state = TXD_IDLE;
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reg [3:0] txd_state = TXD_IDLE;
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reg txd = 1'd1;
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reg txd = 1'd1;
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reg tx_bit_pulse = 'd0;
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reg tx_bit_pulse = 'd0;
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reg [9:0] tx_bit_pulse_count = 'd0;
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reg [9:0] tx_bit_pulse_count = 'd0;
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reg [7:0] rx_byte = 'd0;
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reg [7:0] rx_byte = 'd0;
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reg [3:0] rxd_state = RXD_IDLE;
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reg [3:0] rxd_state = RXD_IDLE;
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wire rx_start;
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wire rx_start;
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reg rxen = 'd0;
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reg rxen = 'd0;
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reg [9:0] rx_bit_pulse_count = 'd0;
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reg [9:0] rx_bit_pulse_count = 'd0;
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reg restart_rx_bit_count = 'd0;
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reg restart_rx_bit_count = 'd0;
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reg [4:0] rxd_d = 5'h1f;
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reg [4:0] rxd_d = 5'h1f;
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reg [3:0] uart0_cts_n_d = 4'hf;
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reg [3:0] uart0_cts_n_d = 4'hf;
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// Wishbone registers
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// Wishbone registers
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reg [7:0] uart_rsr_reg = 'd0; // Receive status, (Write) Error Clear
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reg [7:0] uart_rsr_reg = 'd0; // Receive status, (Write) Error Clear
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reg [7:0] uart_lcrh_reg = 'd0; // Line Control High Byte
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reg [7:0] uart_lcrh_reg = 'd0; // Line Control High Byte
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reg [7:0] uart_lcrm_reg = 'd0; // Line Control Middle Byte
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reg [7:0] uart_lcrm_reg = 'd0; // Line Control Middle Byte
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reg [7:0] uart_lcrl_reg = 'd0; // Line Control Low Byte
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reg [7:0] uart_lcrl_reg = 'd0; // Line Control Low Byte
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reg [7:0] uart_cr_reg = 'd0; // Control Register
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reg [7:0] uart_cr_reg = 'd0; // Control Register
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// Wishbone interface
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// Wishbone interface
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reg [31:0] wb_rdata = 'd0;
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reg [31:0] wb_rdata = 'd0;
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wire wb_start_write;
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wire wb_start_write;
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wire wb_start_read;
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wire wb_start_read;
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reg wb_start_read_d1 = 'd0;
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reg wb_start_read_d1 = 'd0;
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integer i;
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integer i;
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// ======================================================
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// ======================================================
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// Wishbone Interface
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// Wishbone Interface
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// ======================================================
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// ======================================================
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|
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// Can't start a write while a read is completing. The ack for the read cycle
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// Can't start a write while a read is completing. The ack for the read cycle
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// needs to be sent first
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// needs to be sent first
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assign wb_start_write = i_wb_stb && i_wb_we && !wb_start_read_d1;
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assign wb_start_write = i_wb_stb && i_wb_we && !wb_start_read_d1;
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assign wb_start_read = i_wb_stb && !i_wb_we && !o_wb_ack;
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assign wb_start_read = i_wb_stb && !i_wb_we && !o_wb_ack;
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|
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always @( posedge i_clk )
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always @( posedge i_clk )
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wb_start_read_d1 <= wb_start_read;
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wb_start_read_d1 <= wb_start_read;
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|
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assign o_wb_dat = wb_rdata;
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assign o_wb_dat = wb_rdata;
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|
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assign o_wb_err = 1'd0;
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assign o_wb_err = 1'd0;
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assign o_wb_ack = i_wb_stb && ( wb_start_write || wb_start_read_d1 );
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assign o_wb_ack = i_wb_stb && ( wb_start_write || wb_start_read_d1 );
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|
|
|
|
// ======================================================
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// ======================================================
|
// UART 0 Receive FIFO
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// UART 0 Receive FIFO
|
// ======================================================
|
// ======================================================
|
|
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assign rx_fifo_pop = wb_start_read && i_wb_adr[15:0] == AMBER_UART_DR;
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assign rx_fifo_pop = wb_start_read && i_wb_adr[15:0] == AMBER_UART_DR;
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assign rx_fifo_push_not_full = rx_fifo_push && !rx_fifo_full;
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assign rx_fifo_push_not_full = rx_fifo_push && !rx_fifo_full;
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assign rx_fifo_pop_not_empty = rx_fifo_pop && !rx_fifo_empty;
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assign rx_fifo_pop_not_empty = rx_fifo_pop && !rx_fifo_empty;
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assign rx_fifo_half_or_more = rx_fifo_count >= 5'd8;
|
assign rx_fifo_half_or_more = rx_fifo_count >= 5'd8;
|
|
|
|
|
always @ ( posedge i_clk )
|
always @ ( posedge i_clk )
|
begin
|
begin
|
if ( fifo_enable )
|
if ( fifo_enable )
|
begin
|
begin
|
// RX FIFO Push
|
// RX FIFO Push
|
if ( rx_fifo_push_not_full )
|
if ( rx_fifo_push_not_full )
|
begin
|
begin
|
rx_fifo[rx_fifo_wp[3:0]] <= rx_byte;
|
rx_fifo[rx_fifo_wp[3:0]] <= rx_byte;
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rx_fifo_wp <= rx_fifo_wp + 1'd1;
|
rx_fifo_wp <= rx_fifo_wp + 1'd1;
|
end
|
end
|
|
|
if ( rx_fifo_pop_not_empty )
|
if ( rx_fifo_pop_not_empty )
|
begin
|
begin
|
rx_fifo_rp <= rx_fifo_rp + 1'd1;
|
rx_fifo_rp <= rx_fifo_rp + 1'd1;
|
end
|
end
|
|
|
if ( rx_fifo_push_not_full && !rx_fifo_pop_not_empty )
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if ( rx_fifo_push_not_full && !rx_fifo_pop_not_empty )
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rx_fifo_count <= rx_fifo_count + 1'd1;
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rx_fifo_count <= rx_fifo_count + 1'd1;
|
else if ( rx_fifo_pop_not_empty && !rx_fifo_push_not_full )
|
else if ( rx_fifo_pop_not_empty && !rx_fifo_push_not_full )
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rx_fifo_count <= rx_fifo_count - 1'd1;
|
rx_fifo_count <= rx_fifo_count - 1'd1;
|
|
|
rx_fifo_full <= rx_fifo_wp == {~rx_fifo_rp[4], rx_fifo_rp[3:0]};
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rx_fifo_full <= rx_fifo_wp == {~rx_fifo_rp[4], rx_fifo_rp[3:0]};
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rx_fifo_empty <= rx_fifo_wp == rx_fifo_rp;
|
rx_fifo_empty <= rx_fifo_wp == rx_fifo_rp;
|
|
|
if ( rx_fifo_empty || rx_fifo_pop )
|
if ( rx_fifo_empty || rx_fifo_pop )
|
rx_int_timer <= 'd0;
|
rx_int_timer <= 'd0;
|
else if ( rx_int_timer != RX_INTERRUPT_COUNT )
|
else if ( rx_int_timer != RX_INTERRUPT_COUNT )
|
rx_int_timer <= rx_int_timer + 1'd1;
|
rx_int_timer <= rx_int_timer + 1'd1;
|
|
|
|
|
end
|
end
|
else // No FIFO
|
else // No FIFO
|
begin
|
begin
|
rx_int_timer <= 'd0;
|
rx_int_timer <= 'd0;
|
|
|
if ( rx_fifo_push )
|
if ( rx_fifo_push )
|
begin
|
begin
|
rx_fifo[0] <= rx_byte;
|
rx_fifo[0] <= rx_byte;
|
rx_fifo_empty <= 1'd0;
|
rx_fifo_empty <= 1'd0;
|
rx_fifo_full <= 1'd1;
|
rx_fifo_full <= 1'd1;
|
end
|
end
|
else if ( rx_fifo_pop )
|
else if ( rx_fifo_pop )
|
begin
|
begin
|
rx_fifo_empty <= 1'd1;
|
rx_fifo_empty <= 1'd1;
|
rx_fifo_full <= 1'd0;
|
rx_fifo_full <= 1'd0;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
|
|
// ======================================================
|
// ======================================================
|
// Transmit Interrupts
|
// Transmit Interrupts
|
// ======================================================
|
// ======================================================
|
|
|
|
|
// UART 0 Transmit Interrupt
|
// UART 0 Transmit Interrupt
|
always @ ( posedge i_clk )
|
always @ ( posedge i_clk )
|
begin
|
begin
|
// Clear the interrupt
|
// Clear the interrupt
|
if ( wb_start_write && i_wb_adr[15:0] == AMBER_UART_ICR )
|
if ( wb_start_write && i_wb_adr[15:0] == AMBER_UART_ICR )
|
tx_interrupt <= 1'd0;
|
tx_interrupt <= 1'd0;
|
|
|
// Set the interrupt
|
// Set the interrupt
|
else if ( fifo_enable )
|
else if ( fifo_enable )
|
// This interrupt clears automatically as bytes are pushed into the tx fifo
|
// This interrupt clears automatically as bytes are pushed into the tx fifo
|
// cr bit 5 is Transmit Interrupt Enable
|
// cr bit 5 is Transmit Interrupt Enable
|
tx_interrupt <= tx_fifo_half_or_less_full && uart_cr_reg[5];
|
tx_interrupt <= tx_fifo_half_or_less_full && uart_cr_reg[5];
|
else
|
else
|
// This interrupt clears automatically when a byte is written to tx
|
// This interrupt clears automatically when a byte is written to tx
|
// cr bit 5 is Transmit Interrupt Enable
|
// cr bit 5 is Transmit Interrupt Enable
|
tx_interrupt <= tx_fifo_empty && uart_cr_reg[5];
|
tx_interrupt <= tx_fifo_empty && uart_cr_reg[5];
|
end
|
end
|
|
|
|
|
// ======================================================
|
// ======================================================
|
// Receive Interrupts
|
// Receive Interrupts
|
// ======================================================
|
// ======================================================
|
|
|
always @ ( posedge i_clk )
|
always @ ( posedge i_clk )
|
if (fifo_enable)
|
if (fifo_enable)
|
rx_interrupt <= rx_fifo_half_or_more || rx_int_timer == RX_INTERRUPT_COUNT;
|
rx_interrupt <= rx_fifo_half_or_more || rx_int_timer == RX_INTERRUPT_COUNT;
|
else
|
else
|
rx_interrupt <= rx_fifo_full;
|
rx_interrupt <= rx_fifo_full;
|
|
|
|
|
assign o_uart_int = ( tx_interrupt & uart_cr_reg[5] ) | // UART transmit interrupt w/ enable
|
assign o_uart_int = ( tx_interrupt & uart_cr_reg[5] ) | // UART transmit interrupt w/ enable
|
( rx_interrupt & uart_cr_reg[4] ) ; // UART receive interrupt w/ enable
|
( rx_interrupt & uart_cr_reg[4] ) ; // UART receive interrupt w/ enable
|
|
|
assign fifo_enable = uart_lcrh_reg[4];
|
assign fifo_enable = uart_lcrh_reg[4];
|
|
|
|
|
|
|
// ========================================================
|
// ========================================================
|
// UART Transmit
|
// UART Transmit
|
// ========================================================
|
// ========================================================
|
|
|
assign o_uart_txd = txd;
|
assign o_uart_txd = txd;
|
|
|
assign tx_fifo_full = fifo_enable ? tx_fifo_count >= 5'd16 : tx_fifo_full_flag;
|
assign tx_fifo_full = fifo_enable ? tx_fifo_count >= 5'd16 : tx_fifo_full_flag;
|
assign tx_fifo_empty = fifo_enable ? tx_fifo_count == 5'd00 : !tx_fifo_full_flag;
|
assign tx_fifo_empty = fifo_enable ? tx_fifo_count == 5'd00 : !tx_fifo_full_flag;
|
assign tx_fifo_half_or_less_full = tx_fifo_count <= 5'd8;
|
assign tx_fifo_half_or_less_full = tx_fifo_count <= 5'd8;
|
assign tx_byte = fifo_enable ? tx_fifo[tx_fifo_rp[3:0]] : tx_fifo[0] ;
|
assign tx_byte = fifo_enable ? tx_fifo[tx_fifo_rp[3:0]] : tx_fifo[0] ;
|
|
|
assign tx_fifo_push = wb_start_write && i_wb_adr[15:0] == AMBER_UART_DR;
|
assign tx_fifo_push = wb_start_write && i_wb_adr[15:0] == AMBER_UART_DR;
|
assign tx_fifo_push_not_full = tx_fifo_push && !tx_fifo_full;
|
assign tx_fifo_push_not_full = tx_fifo_push && !tx_fifo_full;
|
assign tx_fifo_pop_not_empty = txd_state == TXD_STOP3 && tx_bit_pulse == 1'd1 && !tx_fifo_empty;
|
assign tx_fifo_pop_not_empty = txd_state == TXD_STOP3 && tx_bit_pulse == 1'd1 && !tx_fifo_empty;
|
|
|
|
|
// Transmit FIFO
|
// Transmit FIFO
|
always @( posedge i_clk )
|
always @( posedge i_clk )
|
begin
|
begin
|
// Use 8-entry FIFO
|
// Use 8-entry FIFO
|
if ( fifo_enable )
|
if ( fifo_enable )
|
begin
|
begin
|
// Push
|
// Push
|
if ( tx_fifo_push_not_full )
|
if ( tx_fifo_push_not_full )
|
begin
|
begin
|
tx_fifo[tx_fifo_wp[3:0]] <= i_wb_dat[7:0];
|
tx_fifo[tx_fifo_wp[3:0]] <= i_wb_dat[7:0];
|
tx_fifo_wp <= tx_fifo_wp + 1'd1;
|
tx_fifo_wp <= tx_fifo_wp + 1'd1;
|
end
|
end
|
|
|
|
|
// Pop
|
// Pop
|
if ( tx_fifo_pop_not_empty )
|
if ( tx_fifo_pop_not_empty )
|
tx_fifo_rp <= tx_fifo_rp + 1'd1;
|
tx_fifo_rp <= tx_fifo_rp + 1'd1;
|
|
|
// Count up
|
// Count up
|
if (tx_fifo_push_not_full && !tx_fifo_pop_not_empty)
|
if (tx_fifo_push_not_full && !tx_fifo_pop_not_empty)
|
tx_fifo_count <= tx_fifo_count + 1'd1;
|
tx_fifo_count <= tx_fifo_count + 1'd1;
|
|
|
// Count down
|
// Count down
|
else if (tx_fifo_pop_not_empty && !tx_fifo_push_not_full)
|
else if (tx_fifo_pop_not_empty && !tx_fifo_push_not_full)
|
tx_fifo_count <= tx_fifo_count - 1'd1;
|
tx_fifo_count <= tx_fifo_count - 1'd1;
|
end
|
end
|
|
|
// Do not use 8-entry FIFO, single entry register instead
|
// Do not use 8-entry FIFO, single entry register instead
|
else
|
else
|
begin
|
begin
|
// Clear FIFO values
|
// Clear FIFO values
|
tx_fifo_wp <= 'd0;
|
tx_fifo_wp <= 'd0;
|
tx_fifo_rp <= 'd0;
|
tx_fifo_rp <= 'd0;
|
tx_fifo_count <= 'd0;
|
tx_fifo_count <= 'd0;
|
|
|
// Push
|
// Push
|
if ( tx_fifo_push_not_full )
|
if ( tx_fifo_push_not_full )
|
begin
|
begin
|
tx_fifo[0] <= i_wb_dat[7:0];
|
tx_fifo[0] <= i_wb_dat[7:0];
|
tx_fifo_full_flag <= 1'd1;
|
tx_fifo_full_flag <= 1'd1;
|
end
|
end
|
// Pop
|
// Pop
|
else if ( tx_fifo_pop_not_empty )
|
else if ( tx_fifo_pop_not_empty )
|
tx_fifo_full_flag <= 1'd0;
|
tx_fifo_full_flag <= 1'd0;
|
|
|
end
|
end
|
end
|
end
|
|
|
|
|
// ========================================================
|
// ========================================================
|
// Register Clear to Send Input
|
// Register Clear to Send Input
|
// ========================================================
|
// ========================================================
|
always @( posedge i_clk )
|
always @( posedge i_clk )
|
uart0_cts_n_d <= {uart0_cts_n_d[2:0], i_uart_cts_n};
|
uart0_cts_n_d <= {uart0_cts_n_d[2:0], i_uart_cts_n};
|
|
|
|
|
// ========================================================
|
// ========================================================
|
// Transmit Pulse generater - matches baud rate
|
// Transmit Pulse generater - matches baud rate
|
// ========================================================
|
// ========================================================
|
always @( posedge i_clk )
|
always @( posedge i_clk )
|
if (( tx_bit_pulse_count == (TX_BITADJUST_COUNT-1) && txd_state == TXD_STOP2 ) ||
|
if (( tx_bit_pulse_count == (TX_BITADJUST_COUNT-1) && txd_state == TXD_STOP2 ) ||
|
( tx_bit_pulse_count == (TX_BITPULSE_COUNT-1) && txd_state != TXD_STOP2 ) )
|
( tx_bit_pulse_count == (TX_BITPULSE_COUNT-1) && txd_state != TXD_STOP2 ) )
|
begin
|
begin
|
tx_bit_pulse_count <= 'd0;
|
tx_bit_pulse_count <= 'd0;
|
tx_bit_pulse <= 1'd1;
|
tx_bit_pulse <= 1'd1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
tx_bit_pulse_count <= tx_bit_pulse_count + 1'd1;
|
tx_bit_pulse_count <= tx_bit_pulse_count + 1'd1;
|
tx_bit_pulse <= 1'd0;
|
tx_bit_pulse <= 1'd0;
|
end
|
end
|
|
|
|
|
// ========================================================
|
// ========================================================
|
// Byte Transmitted
|
// Byte Transmitted
|
// ========================================================
|
// ========================================================
|
// Idle state, txd = 1
|
// Idle state, txd = 1
|
// start bit, txd = 0
|
// start bit, txd = 0
|
// Data x 8, lsb first
|
// Data x 8, lsb first
|
// stop bit, txd = 1
|
// stop bit, txd = 1
|
|
|
|
|
// X = 0x58 = 01011000
|
// X = 0x58 = 01011000
|
always @( posedge i_clk )
|
always @( posedge i_clk )
|
if ( tx_bit_pulse )
|
if ( tx_bit_pulse )
|
|
|
case (txd_state)
|
case ( txd_state )
|
|
|
TXD_IDLE :
|
TXD_IDLE :
|
begin
|
begin
|
txd <= 1'd1;
|
txd <= 1'd1;
|
|
|
if ( uart0_cts_n_d[3:1] == 3'b000 && !tx_fifo_empty )
|
if ( uart0_cts_n_d[3:1] == 3'b000 && !tx_fifo_empty )
|
txd_state <= TXD_START;
|
txd_state <= TXD_START;
|
end
|
end
|
|
|
TXD_START :
|
TXD_START :
|
begin
|
begin
|
txd <= 1'd0;
|
txd <= 1'd0;
|
txd_state <= TXD_DATA0;
|
txd_state <= TXD_DATA0;
|
end
|
end
|
|
|
TXD_DATA0 :
|
TXD_DATA0 :
|
begin
|
begin
|
txd <= tx_byte[0];
|
txd <= tx_byte[0];
|
txd_state <= TXD_DATA1;
|
txd_state <= TXD_DATA1;
|
end
|
end
|
|
|
TXD_DATA1 :
|
TXD_DATA1 :
|
begin
|
begin
|
txd <= tx_byte[1];
|
txd <= tx_byte[1];
|
txd_state <= TXD_DATA2;
|
txd_state <= TXD_DATA2;
|
end
|
end
|
|
|
TXD_DATA2 :
|
TXD_DATA2 :
|
begin
|
begin
|
txd <= tx_byte[2];
|
txd <= tx_byte[2];
|
txd_state <= TXD_DATA3;
|
txd_state <= TXD_DATA3;
|
end
|
end
|
|
|
TXD_DATA3 :
|
TXD_DATA3 :
|
begin
|
begin
|
txd <= tx_byte[3];
|
txd <= tx_byte[3];
|
txd_state <= TXD_DATA4;
|
txd_state <= TXD_DATA4;
|
end
|
end
|
|
|
TXD_DATA4 :
|
TXD_DATA4 :
|
begin
|
begin
|
txd <= tx_byte[4];
|
txd <= tx_byte[4];
|
txd_state <= TXD_DATA5;
|
txd_state <= TXD_DATA5;
|
end
|
end
|
|
|
TXD_DATA5 :
|
TXD_DATA5 :
|
begin
|
begin
|
txd <= tx_byte[5];
|
txd <= tx_byte[5];
|
txd_state <= TXD_DATA6;
|
txd_state <= TXD_DATA6;
|
end
|
end
|
|
|
TXD_DATA6 :
|
TXD_DATA6 :
|
begin
|
begin
|
txd <= tx_byte[6];
|
txd <= tx_byte[6];
|
txd_state <= TXD_DATA7;
|
txd_state <= TXD_DATA7;
|
end
|
end
|
|
|
TXD_DATA7 :
|
TXD_DATA7 :
|
begin
|
begin
|
txd <= tx_byte[7];
|
txd <= tx_byte[7];
|
txd_state <= TXD_STOP1;
|
txd_state <= TXD_STOP1;
|
end
|
end
|
|
|
TXD_STOP1 :
|
TXD_STOP1 :
|
begin
|
begin
|
txd <= 1'd1;
|
txd <= 1'd1;
|
txd_state <= TXD_STOP2;
|
txd_state <= TXD_STOP2;
|
end
|
end
|
|
|
TXD_STOP2 :
|
TXD_STOP2 :
|
begin
|
begin
|
txd <= 1'd1;
|
txd <= 1'd1;
|
txd_state <= TXD_STOP3;
|
txd_state <= TXD_STOP3;
|
end
|
end
|
|
|
TXD_STOP3 :
|
TXD_STOP3 :
|
begin
|
begin
|
txd <= 1'd1;
|
txd <= 1'd1;
|
txd_state <= TXD_IDLE;
|
txd_state <= TXD_IDLE;
|
end
|
end
|
|
|
default :
|
default :
|
begin
|
begin
|
txd <= 1'd1;
|
txd <= 1'd1;
|
end
|
end
|
|
|
endcase
|
endcase
|
|
|
|
|
|
|
|
|
// ========================================================
|
// ========================================================
|
// UART Receive
|
// UART Receive
|
// ========================================================
|
// ========================================================
|
|
|
assign o_uart_rts_n = ~rxen;
|
assign o_uart_rts_n = ~rxen;
|
|
|
assign rx_fifo_push = rxd_state == RXD_STOP && rx_bit_pulse_count == 10'd0;
|
assign rx_fifo_push = rxd_state == RXD_STOP && rx_bit_pulse_count == 10'd0;
|
|
|
// ========================================================
|
// ========================================================
|
// Receive bit pulse
|
// Receive bit pulse
|
// ========================================================
|
// ========================================================
|
// Pulse generater - matches baud rate
|
// Pulse generater - matches baud rate
|
always @( posedge i_clk )
|
always @( posedge i_clk )
|
if ( restart_rx_bit_count )
|
if ( restart_rx_bit_count )
|
rx_bit_pulse_count <= 'd0;
|
rx_bit_pulse_count <= 'd0;
|
else
|
else
|
rx_bit_pulse_count <= rx_bit_pulse_count + 1'd1;
|
rx_bit_pulse_count <= rx_bit_pulse_count + 1'd1;
|
|
|
|
|
// ========================================================
|
// ========================================================
|
// Detect 1->0 transition. Filter out glitches and jaggedy transitions
|
// Detect 1->0 transition. Filter out glitches and jaggedy transitions
|
// ========================================================
|
// ========================================================
|
always @( posedge i_clk )
|
always @( posedge i_clk )
|
rxd_d[4:0] <= {rxd_d[3:0], i_uart_rxd};
|
rxd_d[4:0] <= {rxd_d[3:0], i_uart_rxd};
|
|
|
assign rx_start = rxd_d[4:3] == 2'b11 && rxd_d[1:0] == 2'b00;
|
assign rx_start = rxd_d[4:3] == 2'b11 && rxd_d[1:0] == 2'b00;
|
|
|
|
|
// ========================================================
|
// ========================================================
|
// Receive state machine
|
// Receive state machine
|
// ========================================================
|
// ========================================================
|
|
|
always @( posedge i_clk )
|
always @( posedge i_clk )
|
case ( rxd_state )
|
case ( rxd_state )
|
|
|
RXD_IDLE :
|
RXD_IDLE :
|
if ( rx_fifo_full )
|
if ( rx_fifo_full )
|
rxen <= 1'd0;
|
rxen <= 1'd0;
|
else
|
else
|
begin
|
begin
|
rxd_state <= RXD_START;
|
rxd_state <= RXD_START;
|
rxen <= 1'd1;
|
rxen <= 1'd1;
|
restart_rx_bit_count <= 1'd1;
|
restart_rx_bit_count <= 1'd1;
|
rx_byte <= 'd0;
|
rx_byte <= 'd0;
|
end
|
end
|
|
|
RXD_START :
|
RXD_START :
|
// Filter out glitches and jaggedy transitions
|
// Filter out glitches and jaggedy transitions
|
if ( rx_start )
|
if ( rx_start )
|
begin
|
begin
|
rxd_state <= RXD_START_MID;
|
rxd_state <= RXD_START_MID1;
|
restart_rx_bit_count <= 1'd1;
|
restart_rx_bit_count <= 1'd1;
|
end
|
end
|
else
|
else
|
restart_rx_bit_count <= 1'd0;
|
restart_rx_bit_count <= 1'd0;
|
|
|
|
// This state just delays the check on the
|
|
// rx_bit_pulse_count value by 1 clock cycle to
|
|
// give it time to reset
|
|
RXD_START_MID1 :
|
|
rxd_state <= RXD_START_MID;
|
|
|
RXD_START_MID :
|
RXD_START_MID :
|
if ( rx_bit_pulse_count == RX_HALFPULSE_COUNT )
|
if ( rx_bit_pulse_count == RX_HALFPULSE_COUNT )
|
begin
|
begin
|
rxd_state <= RXD_DATA0;
|
rxd_state <= RXD_DATA0;
|
restart_rx_bit_count <= 1'd1;
|
restart_rx_bit_count <= 1'd1;
|
end
|
end
|
else
|
else
|
restart_rx_bit_count <= 1'd0;
|
restart_rx_bit_count <= 1'd0;
|
|
|
RXD_DATA0 :
|
RXD_DATA0 :
|
if ( rx_bit_pulse_count == RX_BITPULSE_COUNT )
|
if ( rx_bit_pulse_count == RX_BITPULSE_COUNT )
|
begin
|
begin
|
rxd_state <= RXD_DATA1;
|
rxd_state <= RXD_DATA1;
|
restart_rx_bit_count <= 1'd1;
|
restart_rx_bit_count <= 1'd1;
|
rx_byte[0] <= i_uart_rxd;
|
rx_byte[0] <= i_uart_rxd;
|
end
|
end
|
else
|
else
|
restart_rx_bit_count <= 1'd0;
|
restart_rx_bit_count <= 1'd0;
|
|
|
RXD_DATA1 :
|
RXD_DATA1 :
|
if ( rx_bit_pulse_count == RX_BITPULSE_COUNT )
|
if ( rx_bit_pulse_count == RX_BITPULSE_COUNT )
|
begin
|
begin
|
rxd_state <= RXD_DATA2;
|
rxd_state <= RXD_DATA2;
|
restart_rx_bit_count <= 1'd1;
|
restart_rx_bit_count <= 1'd1;
|
rx_byte[1] <= i_uart_rxd;
|
rx_byte[1] <= i_uart_rxd;
|
end
|
end
|
else
|
else
|
restart_rx_bit_count <= 1'd0;
|
restart_rx_bit_count <= 1'd0;
|
|
|
RXD_DATA2 :
|
RXD_DATA2 :
|
if ( rx_bit_pulse_count == RX_BITPULSE_COUNT )
|
if ( rx_bit_pulse_count == RX_BITPULSE_COUNT )
|
begin
|
begin
|
rxd_state <= RXD_DATA3;
|
rxd_state <= RXD_DATA3;
|
restart_rx_bit_count <= 1'd1;
|
restart_rx_bit_count <= 1'd1;
|
rx_byte[2] <= i_uart_rxd;
|
rx_byte[2] <= i_uart_rxd;
|
end
|
end
|
else
|
else
|
restart_rx_bit_count <= 1'd0;
|
restart_rx_bit_count <= 1'd0;
|
|
|
RXD_DATA3 :
|
RXD_DATA3 :
|
if ( rx_bit_pulse_count == RX_BITPULSE_COUNT )
|
if ( rx_bit_pulse_count == RX_BITPULSE_COUNT )
|
begin
|
begin
|
rxd_state <= RXD_DATA4;
|
rxd_state <= RXD_DATA4;
|
restart_rx_bit_count <= 1'd1;
|
restart_rx_bit_count <= 1'd1;
|
rx_byte[3] <= i_uart_rxd;
|
rx_byte[3] <= i_uart_rxd;
|
end
|
end
|
else
|
else
|
restart_rx_bit_count <= 1'd0;
|
restart_rx_bit_count <= 1'd0;
|
|
|
RXD_DATA4 :
|
RXD_DATA4 :
|
if ( rx_bit_pulse_count == RX_BITPULSE_COUNT )
|
if ( rx_bit_pulse_count == RX_BITPULSE_COUNT )
|
begin
|
begin
|
rxd_state <= RXD_DATA5;
|
rxd_state <= RXD_DATA5;
|
restart_rx_bit_count <= 1'd1;
|
restart_rx_bit_count <= 1'd1;
|
rx_byte[4] <= i_uart_rxd;
|
rx_byte[4] <= i_uart_rxd;
|
end
|
end
|
else
|
else
|
restart_rx_bit_count <= 1'd0;
|
restart_rx_bit_count <= 1'd0;
|
|
|
RXD_DATA5 :
|
RXD_DATA5 :
|
if ( rx_bit_pulse_count == RX_BITPULSE_COUNT )
|
if ( rx_bit_pulse_count == RX_BITPULSE_COUNT )
|
begin
|
begin
|
rxd_state <= RXD_DATA6;
|
rxd_state <= RXD_DATA6;
|
restart_rx_bit_count <= 1'd1;
|
restart_rx_bit_count <= 1'd1;
|
rx_byte[5] <= i_uart_rxd;
|
rx_byte[5] <= i_uart_rxd;
|
end
|
end
|
else
|
else
|
restart_rx_bit_count <= 1'd0;
|
restart_rx_bit_count <= 1'd0;
|
|
|
RXD_DATA6 :
|
RXD_DATA6 :
|
if ( rx_bit_pulse_count == RX_BITPULSE_COUNT )
|
if ( rx_bit_pulse_count == RX_BITPULSE_COUNT )
|
begin
|
begin
|
rxd_state <= RXD_DATA7;
|
rxd_state <= RXD_DATA7;
|
restart_rx_bit_count <= 1'd1;
|
restart_rx_bit_count <= 1'd1;
|
rx_byte[6] <= i_uart_rxd;
|
rx_byte[6] <= i_uart_rxd;
|
end
|
end
|
else
|
else
|
restart_rx_bit_count <= 1'd0;
|
restart_rx_bit_count <= 1'd0;
|
|
|
RXD_DATA7 :
|
RXD_DATA7 :
|
if ( rx_bit_pulse_count == RX_BITPULSE_COUNT )
|
if ( rx_bit_pulse_count == RX_BITPULSE_COUNT )
|
begin
|
begin
|
rxd_state <= RXD_STOP;
|
rxd_state <= RXD_STOP;
|
restart_rx_bit_count <= 1'd1;
|
restart_rx_bit_count <= 1'd1;
|
rx_byte[7] <= i_uart_rxd;
|
rx_byte[7] <= i_uart_rxd;
|
end
|
end
|
else
|
else
|
restart_rx_bit_count <= 1'd0;
|
restart_rx_bit_count <= 1'd0;
|
|
|
RXD_STOP :
|
RXD_STOP :
|
if ( rx_bit_pulse_count == RX_BITPULSE_COUNT ) // half way through stop bit
|
if ( rx_bit_pulse_count == RX_BITPULSE_COUNT ) // half way through stop bit
|
begin
|
begin
|
rxd_state <= RXD_IDLE;
|
rxd_state <= RXD_IDLE;
|
restart_rx_bit_count <= 1'd1;
|
restart_rx_bit_count <= 1'd1;
|
end
|
end
|
else
|
else
|
restart_rx_bit_count <= 1'd0;
|
restart_rx_bit_count <= 1'd0;
|
|
|
default :
|
default :
|
begin
|
begin
|
rxd_state <= RXD_IDLE;
|
rxd_state <= RXD_IDLE;
|
end
|
end
|
|
|
endcase
|
endcase
|
|
|
|
|
// ========================================================
|
// ========================================================
|
// Register Writes
|
// Register Writes
|
// ========================================================
|
// ========================================================
|
always @( posedge i_clk )
|
always @( posedge i_clk )
|
if ( wb_start_write )
|
if ( wb_start_write )
|
case ( i_wb_adr[15:0] )
|
case ( i_wb_adr[15:0] )
|
// Receive status, (Write) Error Clear
|
// Receive status, (Write) Error Clear
|
AMBER_UART_RSR: uart_rsr_reg <= i_wb_dat[7:0];
|
AMBER_UART_RSR: uart_rsr_reg <= i_wb_dat[7:0];
|
// Line Control High Byte
|
// Line Control High Byte
|
AMBER_UART_LCRH: uart_lcrh_reg <= i_wb_dat[7:0];
|
AMBER_UART_LCRH: uart_lcrh_reg <= i_wb_dat[7:0];
|
// Line Control Middle Byte
|
// Line Control Middle Byte
|
AMBER_UART_LCRM: uart_lcrm_reg <= i_wb_dat[7:0];
|
AMBER_UART_LCRM: uart_lcrm_reg <= i_wb_dat[7:0];
|
// Line Control Low Byte
|
// Line Control Low Byte
|
AMBER_UART_LCRL: uart_lcrl_reg <= i_wb_dat[7:0];
|
AMBER_UART_LCRL: uart_lcrl_reg <= i_wb_dat[7:0];
|
// Control Register
|
// Control Register
|
AMBER_UART_CR: uart_cr_reg <= i_wb_dat[7:0];
|
AMBER_UART_CR: uart_cr_reg <= i_wb_dat[7:0];
|
endcase
|
endcase
|
|
|
|
|
// ========================================================
|
// ========================================================
|
// Register Reads
|
// Register Reads
|
// ========================================================
|
// ========================================================
|
always @( posedge i_clk )
|
always @( posedge i_clk )
|
if ( wb_start_read )
|
if ( wb_start_read )
|
case ( i_wb_adr[15:0] )
|
case ( i_wb_adr[15:0] )
|
|
|
AMBER_UART_CID0: wb_rdata <= 32'h0d;
|
AMBER_UART_CID0: wb_rdata <= 32'h0d;
|
AMBER_UART_CID1: wb_rdata <= 32'hf0;
|
AMBER_UART_CID1: wb_rdata <= 32'hf0;
|
AMBER_UART_CID2: wb_rdata <= 32'h05;
|
AMBER_UART_CID2: wb_rdata <= 32'h05;
|
AMBER_UART_CID3: wb_rdata <= 32'hb1;
|
AMBER_UART_CID3: wb_rdata <= 32'hb1;
|
AMBER_UART_PID0: wb_rdata <= 32'h10;
|
AMBER_UART_PID0: wb_rdata <= 32'h10;
|
AMBER_UART_PID1: wb_rdata <= 32'h10;
|
AMBER_UART_PID1: wb_rdata <= 32'h10;
|
AMBER_UART_PID2: wb_rdata <= 32'h04;
|
AMBER_UART_PID2: wb_rdata <= 32'h04;
|
AMBER_UART_PID3: wb_rdata <= 32'h00;
|
AMBER_UART_PID3: wb_rdata <= 32'h00;
|
|
|
AMBER_UART_DR: // Rx data
|
AMBER_UART_DR: // Rx data
|
if ( fifo_enable )
|
if ( fifo_enable )
|
wb_rdata <= {24'd0, rx_fifo[rx_fifo_rp[3:0]]};
|
wb_rdata <= {24'd0, rx_fifo[rx_fifo_rp[3:0]]};
|
else
|
else
|
wb_rdata <= {24'd0, rx_fifo[0]};
|
wb_rdata <= {24'd0, rx_fifo[0]};
|
|
|
AMBER_UART_RSR: wb_rdata <= uart_rsr_reg; // Receive status, (Write) Error Clear
|
AMBER_UART_RSR: wb_rdata <= uart_rsr_reg; // Receive status, (Write) Error Clear
|
AMBER_UART_LCRH: wb_rdata <= uart_lcrh_reg; // Line Control High Byte
|
AMBER_UART_LCRH: wb_rdata <= uart_lcrh_reg; // Line Control High Byte
|
AMBER_UART_LCRM: wb_rdata <= uart_lcrm_reg; // Line Control Middle Byte
|
AMBER_UART_LCRM: wb_rdata <= uart_lcrm_reg; // Line Control Middle Byte
|
AMBER_UART_LCRL: wb_rdata <= uart_lcrl_reg; // Line Control Low Byte
|
AMBER_UART_LCRL: wb_rdata <= uart_lcrl_reg; // Line Control Low Byte
|
AMBER_UART_CR: wb_rdata <= uart_cr_reg; // Control Register
|
AMBER_UART_CR: wb_rdata <= uart_cr_reg; // Control Register
|
|
|
// UART Tx/Rx Status
|
// UART Tx/Rx Status
|
AMBER_UART_FR: wb_rdata <= {tx_fifo_empty, // tx fifo empty
|
AMBER_UART_FR: wb_rdata <= {tx_fifo_empty, // tx fifo empty
|
rx_fifo_full, // rx fifo full
|
rx_fifo_full, // rx fifo full
|
tx_fifo_full, // tx fifo full
|
tx_fifo_full, // tx fifo full
|
rx_fifo_empty, // rx fifo empty
|
rx_fifo_empty, // rx fifo empty
|
!tx_fifo_empty, // uart busy
|
!tx_fifo_empty, // uart busy
|
1'd1, // !Data Carrier Detect
|
1'd1, // !Data Carrier Detect
|
1'd1, // !Data Set Ready
|
1'd1, // !Data Set Ready
|
!uart0_cts_n_d[3] // !Clear to Send
|
!uart0_cts_n_d[3] // !Clear to Send
|
}; // Flag Register
|
}; // Flag Register
|
|
|
// Interrupt Status
|
// Interrupt Status
|
AMBER_UART_IIR: wb_rdata <= {5'd0,
|
AMBER_UART_IIR: wb_rdata <= {5'd0,
|
1'd0, // RTIS - receive timeout interrupt
|
1'd0, // RTIS - receive timeout interrupt
|
tx_interrupt, // TIS - transmit interrupt status
|
tx_interrupt, // TIS - transmit interrupt status
|
rx_interrupt, // RIS - receive interrupt status
|
rx_interrupt, // RIS - receive interrupt status
|
1'd0 // Modem interrupt status
|
1'd0 // Modem interrupt status
|
}; // (Write) Clear Int
|
}; // (Write) Clear Int
|
|
|
default: wb_rdata <= 32'h00c0ffee;
|
default: wb_rdata <= 32'h00c0ffee;
|
|
|
endcase
|
endcase
|
|
|
|
|
|
|
|
|
// =======================================================================================
|
// =======================================================================================
|
// =======================================================================================
|
// =======================================================================================
|
// =======================================================================================
|
// =======================================================================================
|
// Non-synthesizable debug code
|
// Non-synthesizable debug code
|
// =======================================================================================
|
// =======================================================================================
|
|
|
|
|
//synopsys translate_off
|
//synopsys translate_off
|
|
|
// ========================================================
|
// ========================================================
|
// Report UART Register accesses
|
// Report UART Register accesses
|
// ========================================================
|
// ========================================================
|
|
|
`ifndef Veritak
|
`ifndef Veritak
|
// Check in case UART approximate period
|
// Check in case UART approximate period
|
// is too far off
|
// is too far off
|
initial
|
initial
|
begin
|
begin
|
if ((( TX_BITPULSE_COUNT * CLK_PERIOD ) > (UART_BIT_PERIOD * 1.03) ) ||
|
if ((( TX_BITPULSE_COUNT * CLK_PERIOD ) > (UART_BIT_PERIOD * 1.03) ) ||
|
(( TX_BITPULSE_COUNT * CLK_PERIOD ) < (UART_BIT_PERIOD * 0.97) ) )
|
(( TX_BITPULSE_COUNT * CLK_PERIOD ) < (UART_BIT_PERIOD * 0.97) ) )
|
begin
|
begin
|
`TB_ERROR_MESSAGE
|
`TB_ERROR_MESSAGE
|
$display("UART TX bit period, %.1f, is too big. UART will not work!", TX_BITPULSE_COUNT * CLK_PERIOD);
|
$display("UART TX bit period, %.1f, is too big. UART will not work!", TX_BITPULSE_COUNT * CLK_PERIOD);
|
$display("Baud rate is %d, and baud bit period is %.1f", UART_BAUD, UART_BIT_PERIOD);
|
$display("Baud rate is %d, and baud bit period is %.1f", UART_BAUD, UART_BIT_PERIOD);
|
$display("Either reduce the baud rate, or increase the system clock frequency");
|
$display("Either reduce the baud rate, or increase the system clock frequency");
|
$display("------");
|
$display("------");
|
end
|
end
|
end
|
end
|
`endif
|
`endif
|
|
|
|
|
`ifdef AMBER_UART_DEBUG
|
`ifdef AMBER_UART_DEBUG
|
wire wb_read_ack;
|
wire wb_read_ack;
|
reg uart0_rx_int_d1 = 'd0;
|
reg uart0_rx_int_d1 = 'd0;
|
|
|
assign wb_read_ack = i_wb_stb && !i_wb_we && o_wb_ack;
|
assign wb_read_ack = i_wb_stb && !i_wb_we && o_wb_ack;
|
|
|
`ifndef Veritak
|
`ifndef Veritak
|
initial
|
initial
|
begin
|
begin
|
$display("%m UART period = %f nS, want %f nS, %d, %d",
|
$display("%m UART period = %f nS, want %f nS, %d, %d",
|
(TX_BITPULSE_COUNT*11 + TX_BITADJUST_COUNT) * CLK_PERIOD,
|
(TX_BITPULSE_COUNT*11 + TX_BITADJUST_COUNT) * CLK_PERIOD,
|
UART_WORD_PERIOD,
|
UART_WORD_PERIOD,
|
TX_BITPULSE_COUNT, TX_BITADJUST_COUNT);
|
TX_BITPULSE_COUNT, TX_BITADJUST_COUNT);
|
end
|
end
|
`endif
|
`endif
|
|
|
|
|
// Transmit Interrupts
|
// Transmit Interrupts
|
always @ ( posedge i_clk )
|
always @ ( posedge i_clk )
|
if ( wb_start_write && i_wb_adr[15:0] == AMBER_UART_ICR )
|
if ( wb_start_write && i_wb_adr[15:0] == AMBER_UART_ICR )
|
;
|
;
|
else if ( fifo_enable )
|
else if ( fifo_enable )
|
begin
|
begin
|
if (tx_interrupt == 1'd0 && tx_fifo_half_or_less_full && uart_cr_reg[5])
|
if (tx_interrupt == 1'd0 && tx_fifo_half_or_less_full && uart_cr_reg[5])
|
$display("%m: tx_interrupt Interrupt Set with FIFO enabled");
|
$display("%m: tx_interrupt Interrupt Set with FIFO enabled");
|
if (tx_interrupt == 1'd1 && !(tx_fifo_half_or_less_full && uart_cr_reg[5]))
|
if (tx_interrupt == 1'd1 && !(tx_fifo_half_or_less_full && uart_cr_reg[5]))
|
$display("%m: tx_interrupt Interrupt Cleared with FIFO enabled");
|
$display("%m: tx_interrupt Interrupt Cleared with FIFO enabled");
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if (tx_interrupt == 1'd0 && tx_fifo_empty && uart_cr_reg[5])
|
if (tx_interrupt == 1'd0 && tx_fifo_empty && uart_cr_reg[5])
|
$display("%m: tx_interrupt Interrupt Set with FIFO disabled");
|
$display("%m: tx_interrupt Interrupt Set with FIFO disabled");
|
if (tx_interrupt == 1'd1 && !(tx_fifo_empty && uart_cr_reg[5]))
|
if (tx_interrupt == 1'd1 && !(tx_fifo_empty && uart_cr_reg[5]))
|
$display("%m: tx_interrupt Interrupt Cleared with FIFO disabled");
|
$display("%m: tx_interrupt Interrupt Cleared with FIFO disabled");
|
end
|
end
|
|
|
|
|
// Receive Interrupts
|
// Receive Interrupts
|
always @ ( posedge i_clk )
|
always @ ( posedge i_clk )
|
begin
|
begin
|
uart0_rx_int_d1 <= rx_interrupt;
|
uart0_rx_int_d1 <= rx_interrupt;
|
|
|
if ( rx_interrupt && !uart0_rx_int_d1 )
|
if ( rx_interrupt && !uart0_rx_int_d1 )
|
begin
|
begin
|
`TB_DEBUG_MESSAGE
|
`TB_DEBUG_MESSAGE
|
$display("rx_interrupt Interrupt fifo_enable %d, rx_fifo_full %d",
|
$display("rx_interrupt Interrupt fifo_enable %d, rx_fifo_full %d",
|
fifo_enable, rx_fifo_full);
|
fifo_enable, rx_fifo_full);
|
$display("rx_fifo_half_or_more %d, rx_int_timer 0x%08h, rx_fifo_count %d",
|
$display("rx_fifo_half_or_more %d, rx_int_timer 0x%08h, rx_fifo_count %d",
|
rx_fifo_half_or_more, rx_int_timer, rx_fifo_count);
|
rx_fifo_half_or_more, rx_int_timer, rx_fifo_count);
|
end
|
end
|
|
|
if ( !rx_interrupt && uart0_rx_int_d1 )
|
if ( !rx_interrupt && uart0_rx_int_d1 )
|
begin
|
begin
|
`TB_DEBUG_MESSAGE
|
`TB_DEBUG_MESSAGE
|
$display("rx_interrupt Interrupt Cleared fifo_enable %d, rx_fifo_full %d",
|
$display("rx_interrupt Interrupt Cleared fifo_enable %d, rx_fifo_full %d",
|
fifo_enable, rx_fifo_full);
|
fifo_enable, rx_fifo_full);
|
$display(" rx_fifo_half_or_more %d, rx_int_timer 0x%08h, rx_fifo_count %d",
|
$display(" rx_fifo_half_or_more %d, rx_int_timer 0x%08h, rx_fifo_count %d",
|
rx_fifo_half_or_more, rx_int_timer, rx_fifo_count);
|
rx_fifo_half_or_more, rx_int_timer, rx_fifo_count);
|
end
|
end
|
end
|
end
|
|
|
|
|
always @( posedge i_clk )
|
always @( posedge i_clk )
|
if ( wb_read_ack || wb_start_write )
|
if ( wb_read_ack || wb_start_write )
|
begin
|
begin
|
`TB_DEBUG_MESSAGE
|
`TB_DEBUG_MESSAGE
|
|
|
if ( wb_start_write )
|
if ( wb_start_write )
|
$write("Write 0x%08x to ", i_wb_dat);
|
$write("Write 0x%08x to ", i_wb_dat);
|
else
|
else
|
$write("Read 0x%08x from ", o_wb_dat);
|
$write("Read 0x%08x from ", o_wb_dat);
|
|
|
case ( i_wb_adr[15:0] )
|
case ( i_wb_adr[15:0] )
|
AMBER_UART_PID0: $write("UART PID0 register");
|
AMBER_UART_PID0: $write("UART PID0 register");
|
AMBER_UART_PID1: $write("UART PID1 register");
|
AMBER_UART_PID1: $write("UART PID1 register");
|
AMBER_UART_PID2: $write("UART PID2 register");
|
AMBER_UART_PID2: $write("UART PID2 register");
|
AMBER_UART_PID3: $write("UART PID3 register");
|
AMBER_UART_PID3: $write("UART PID3 register");
|
AMBER_UART_CID0: $write("UART CID0 register");
|
AMBER_UART_CID0: $write("UART CID0 register");
|
AMBER_UART_CID1: $write("UART CID1 register");
|
AMBER_UART_CID1: $write("UART CID1 register");
|
AMBER_UART_CID2: $write("UART CID2 register");
|
AMBER_UART_CID2: $write("UART CID2 register");
|
AMBER_UART_CID3: $write("UART CID3 register");
|
AMBER_UART_CID3: $write("UART CID3 register");
|
AMBER_UART_DR: $write("UART Tx/Rx char %c", wb_start_write ? i_wb_dat[7:0] : o_wb_dat[7:0] );
|
AMBER_UART_DR: $write("UART Tx/Rx char %c", wb_start_write ? i_wb_dat[7:0] : o_wb_dat[7:0] );
|
AMBER_UART_RSR: $write("UART (Read) Receive status, (Write) Error Clear");
|
AMBER_UART_RSR: $write("UART (Read) Receive status, (Write) Error Clear");
|
AMBER_UART_LCRH: $write("UART Line Control High Byte");
|
AMBER_UART_LCRH: $write("UART Line Control High Byte");
|
AMBER_UART_LCRM: $write("UART Line Control Middle Byte");
|
AMBER_UART_LCRM: $write("UART Line Control Middle Byte");
|
AMBER_UART_LCRL: $write("UART Line Control Low Byte");
|
AMBER_UART_LCRL: $write("UART Line Control Low Byte");
|
AMBER_UART_CR: $write("UART Control Register");
|
AMBER_UART_CR: $write("UART Control Register");
|
AMBER_UART_FR: $write("UART Flag Register");
|
AMBER_UART_FR: $write("UART Flag Register");
|
AMBER_UART_IIR: $write("UART (Read) Interrupt Identification Register");
|
AMBER_UART_IIR: $write("UART (Read) Interrupt Identification Register");
|
|
|
default:
|
default:
|
begin
|
begin
|
`TB_ERROR_MESSAGE
|
`TB_ERROR_MESSAGE
|
$write("Unknown UART Register region");
|
$write("Unknown UART Register region");
|
end
|
end
|
endcase
|
endcase
|
|
|
$write(", Address 0x%08h\n", i_wb_adr);
|
$write(", Address 0x%08h\n", i_wb_adr);
|
end
|
end
|
`endif
|
`endif
|
|
|
|
|
// ========================================================
|
// ========================================================
|
// Assertions
|
// Assertions
|
// ========================================================
|
// ========================================================
|
always @ ( posedge i_clk )
|
always @ ( posedge i_clk )
|
begin
|
begin
|
if ( rx_fifo_pop && !rx_fifo_push && rx_fifo_empty )
|
if ( rx_fifo_pop && !rx_fifo_push && rx_fifo_empty )
|
begin
|
begin
|
`TB_WARNING_MESSAGE
|
`TB_WARNING_MESSAGE
|
$write("UART rx FIFO underflow\n");
|
$write("UART rx FIFO underflow\n");
|
end
|
end
|
if ( !rx_fifo_pop && rx_fifo_push && rx_fifo_full )
|
if ( !rx_fifo_pop && rx_fifo_push && rx_fifo_full )
|
begin
|
begin
|
`TB_WARNING_MESSAGE
|
`TB_WARNING_MESSAGE
|
$write("UART rx FIFO overflow\n");
|
$write("UART rx FIFO overflow\n");
|
end
|
end
|
|
|
if ( tx_fifo_push && tx_fifo_full )
|
if ( tx_fifo_push && tx_fifo_full )
|
begin
|
begin
|
`TB_WARNING_MESSAGE
|
`TB_WARNING_MESSAGE
|
$display("UART tx FIFO overflow - char = %c", i_wb_dat[7:0]);
|
$display("UART tx FIFO overflow - char = %c", i_wb_dat[7:0]);
|
end
|
end
|
end
|
end
|
|
|
|
|
// ========================================================
|
// ========================================================
|
// Debug State Machines
|
// Debug State Machines
|
// ========================================================
|
// ========================================================
|
|
|
wire [(10*8)-1:0] xTXD_STATE;
|
wire [(10*8)-1:0] xTXD_STATE;
|
wire [(14*8)-1:0] xRXD_STATE;
|
wire [(14*8)-1:0] xRXD_STATE;
|
|
|
|
|
assign xTXD_STATE = txd_state == TXD_IDLE ? "TXD_IDLE" :
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assign xTXD_STATE = txd_state == TXD_IDLE ? "TXD_IDLE" :
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txd_state == TXD_START ? "TXD_START" :
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txd_state == TXD_START ? "TXD_START" :
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txd_state == TXD_DATA0 ? "TXD_DATA0" :
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txd_state == TXD_DATA0 ? "TXD_DATA0" :
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txd_state == TXD_DATA1 ? "TXD_DATA1" :
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txd_state == TXD_DATA1 ? "TXD_DATA1" :
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txd_state == TXD_DATA2 ? "TXD_DATA2" :
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txd_state == TXD_DATA2 ? "TXD_DATA2" :
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txd_state == TXD_DATA3 ? "TXD_DATA3" :
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txd_state == TXD_DATA3 ? "TXD_DATA3" :
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txd_state == TXD_DATA4 ? "TXD_DATA4" :
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txd_state == TXD_DATA4 ? "TXD_DATA4" :
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txd_state == TXD_DATA5 ? "TXD_DATA5" :
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txd_state == TXD_DATA5 ? "TXD_DATA5" :
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txd_state == TXD_DATA6 ? "TXD_DATA6" :
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txd_state == TXD_DATA6 ? "TXD_DATA6" :
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txd_state == TXD_DATA7 ? "TXD_DATA7" :
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txd_state == TXD_DATA7 ? "TXD_DATA7" :
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txd_state == TXD_STOP1 ? "TXD_STOP1" :
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txd_state == TXD_STOP1 ? "TXD_STOP1" :
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txd_state == TXD_STOP2 ? "TXD_STOP2" :
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txd_state == TXD_STOP2 ? "TXD_STOP2" :
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txd_state == TXD_STOP3 ? "TXD_STOP3" :
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txd_state == TXD_STOP3 ? "TXD_STOP3" :
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"UNKNOWN" ;
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"UNKNOWN" ;
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assign xRXD_STATE = rxd_state == RXD_IDLE ? "RXD_IDLE" :
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assign xRXD_STATE = rxd_state == RXD_IDLE ? "RXD_IDLE" :
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rxd_state == RXD_START ? "RXD_START" :
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rxd_state == RXD_START ? "RXD_START" :
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rxd_state == RXD_START_MID1 ? "RXD_START_MID1":
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rxd_state == RXD_START_MID ? "RXD_START_MID" :
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rxd_state == RXD_START_MID ? "RXD_START_MID" :
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rxd_state == RXD_DATA0 ? "RXD_DATA0" :
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rxd_state == RXD_DATA0 ? "RXD_DATA0" :
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rxd_state == RXD_DATA1 ? "RXD_DATA1" :
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rxd_state == RXD_DATA1 ? "RXD_DATA1" :
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rxd_state == RXD_DATA2 ? "RXD_DATA2" :
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rxd_state == RXD_DATA2 ? "RXD_DATA2" :
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rxd_state == RXD_DATA3 ? "RXD_DATA3" :
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rxd_state == RXD_DATA3 ? "RXD_DATA3" :
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rxd_state == RXD_DATA4 ? "RXD_DATA4" :
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rxd_state == RXD_DATA4 ? "RXD_DATA4" :
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rxd_state == RXD_DATA5 ? "RXD_DATA5" :
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rxd_state == RXD_DATA5 ? "RXD_DATA5" :
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rxd_state == RXD_DATA6 ? "RXD_DATA6" :
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rxd_state == RXD_DATA6 ? "RXD_DATA6" :
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rxd_state == RXD_DATA7 ? "RXD_DATA7" :
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rxd_state == RXD_DATA7 ? "RXD_DATA7" :
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rxd_state == RXD_STOP ? "RXD_STOP" :
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rxd_state == RXD_STOP ? "RXD_STOP" :
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"UNKNOWN" ;
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"UNKNOWN" ;
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//synopsys translate_on
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//synopsys translate_on
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endmodule
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endmodule
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