| Line 52... |
Line 52... |
`ifdef XILINX_VIRTEX6_FPGA
|
`ifdef XILINX_VIRTEX6_FPGA
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reg clk_533mhz;
|
reg clk_533mhz;
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`endif
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`endif
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reg clk_200mhz;
|
reg clk_200mhz;
|
reg clk_25mhz;
|
reg clk_25mhz;
|
reg [31:0] clk_count;
|
reg [31:0] clk_count = 'd0;
|
|
|
integer log_file;
|
integer log_file;
|
|
|
`ifdef AMBER_LOAD_MAIN_MEM
|
`ifdef AMBER_LOAD_MAIN_MEM
|
integer main_mem_file;
|
integer main_mem_file;
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| Line 252... |
Line 252... |
end
|
end
|
|
|
initial
|
initial
|
begin
|
begin
|
sysrst = 1'd1;
|
sysrst = 1'd1;
|
#15002500
|
#40000
|
sysrst = 1'd0;
|
sysrst = 1'd0;
|
end
|
end
|
|
|
|
|
// ======================================
|
// ======================================
|
// Counter of system clock ticks
|
// Counter of system clock ticks
|
// ======================================
|
// ======================================
|
always @ ( posedge `U_SYSTEM.sys_clk )
|
always @ ( posedge `U_SYSTEM.sys_clk )
|
if ( `U_SYSTEM.sys_rst )
|
|
clk_count <= 'd0;
|
|
else
|
|
clk_count <= clk_count + 1'd1;
|
clk_count <= clk_count + 1'd1;
|
|
|
|
|
|
|
// ======================================
|
// ======================================
|
| Line 435... |
Line 432... |
dumpvcd u_dumpvcd();
|
dumpvcd u_dumpvcd();
|
|
|
// ======================================
|
// ======================================
|
// Terminate Test
|
// Terminate Test
|
// ======================================
|
// ======================================
|
`include "amber_localparams.v"
|
`ifdef AMBER_A25_CORE
|
`include "amber_functions.v"
|
`include "a25_localparams.v"
|
|
`include "a25_functions.v"
|
|
`else
|
|
`include "a23_localparams.v"
|
|
`include "a23_functions.v"
|
|
`endif
|
|
|
reg testfail;
|
reg testfail;
|
wire test_status_set;
|
wire test_status_set;
|
wire [31:0] test_status_reg;
|
wire [31:0] test_status_reg;
|
|
|
| Line 456... |
Line 458... |
begin
|
begin
|
if ( test_status_reg == 32'd17 && !testfail )
|
if ( test_status_reg == 32'd17 && !testfail )
|
begin
|
begin
|
display_registers;
|
display_registers;
|
$display("++++++++++++++++++++");
|
$display("++++++++++++++++++++");
|
$write("Passed %s\n", `AMBER_TEST_NAME);
|
$write("Passed %s %0d ticks\n", `AMBER_TEST_NAME, `U_TB.clk_count);
|
$display("++++++++++++++++++++");
|
$display("++++++++++++++++++++");
|
$fwrite(`U_TB.log_file,"Passed %s\n", `AMBER_TEST_NAME);
|
$fwrite(`U_TB.log_file,"Passed %s %0d ticks\n", `AMBER_TEST_NAME, `U_TB.clk_count);
|
$finish;
|
$finish;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
display_registers;
|
display_registers;
|
if ( testfail )
|
if ( testfail )
|
begin
|
begin
|
$display("++++++++++++++++++++");
|
$display("++++++++++++++++++++");
|
$write("Failed %s - assertion error\n", `AMBER_TEST_NAME);
|
$write("Failed %s\n", `AMBER_TEST_NAME);
|
$display("++++++++++++++++++++");
|
$display("++++++++++++++++++++");
|
$fwrite(`U_TB.log_file,"Failed %s - assertion error\n", `AMBER_TEST_NAME);
|
$fwrite(`U_TB.log_file,"Failed %s\n", `AMBER_TEST_NAME);
|
$finish;
|
$finish;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
$display("++++++++++++++++++++");
|
$display("++++++++++++++++++++");
|
| Line 491... |
Line 493... |
end
|
end
|
end
|
end
|
end
|
end
|
|
|
|
|
|
// ======================================
|
|
// Timeout
|
|
// ======================================
|
|
always @ ( posedge `U_SYSTEM.sys_clk )
|
|
if ( `AMBER_TIMEOUT != 0 )
|
|
if (`U_TB.clk_count >= `AMBER_TIMEOUT)
|
|
begin
|
|
`TB_ERROR_MESSAGE
|
|
$display("Timeout Error");
|
|
end
|
|
|
// ======================================
|
// ======================================
|
// Tasks
|
// Tasks
|
// ======================================
|
// ======================================
|
task display_registers;
|
task display_registers;
|
| Line 568... |
Line 580... |
2'd3: insert_32_into_128 = {word32, word128[95:0]};
|
2'd3: insert_32_into_128 = {word32, word128[95:0]};
|
endcase
|
endcase
|
end
|
end
|
endfunction
|
endfunction
|
|
|
endmodule
|
|
|
|
|
|
|
|
|
|
module WireDelay # (
|
|
parameter Delay_g = 0,
|
|
parameter Delay_rd = 0
|
|
)
|
|
(
|
|
inout A,
|
|
inout B,
|
|
input reset
|
|
);
|
|
|
|
reg A_r;
|
|
reg B_r;
|
|
reg line_en;
|
|
|
|
assign A = A_r;
|
|
assign B = B_r;
|
|
|
|
always @(*) begin
|
|
if (!reset) begin
|
|
A_r <= 1'bz;
|
|
B_r <= 1'bz;
|
|
line_en <= 1'b0;
|
|
end else begin
|
|
if (line_en) begin
|
|
A_r <= #Delay_rd B;
|
|
B_r <= 1'bz;
|
|
end else begin
|
|
B_r <= #Delay_g A;
|
|
A_r <= 1'bz;
|
|
end
|
|
end
|
|
end
|
|
|
|
always @(A or B) begin
|
|
if (!reset) begin
|
|
line_en <= 1'b0;
|
|
end else if (A !== A_r) begin
|
|
line_en <= 1'b0;
|
|
end else if (B_r !== B) begin
|
|
line_en <= 1'b1;
|
|
end else begin
|
|
line_en <= line_en;
|
|
end
|
|
end
|
|
endmodule
|
endmodule
|
|
|
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