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module tb();
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module tb();
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`include "debug_functions.v"
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`include "debug_functions.v"
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`include "system_functions.v"
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`include "system_functions.v"
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`include "memory_configuration.v"
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reg sysrst;
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reg sysrst;
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`ifdef XILINX_VIRTEX6_FPGA
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`ifdef XILINX_VIRTEX6_FPGA
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reg clk_533mhz;
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reg clk_533mhz;
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`endif
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`endif
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`ifdef XILINX_SPARTAN6_FPGA
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`ifdef XILINX_SPARTAN6_FPGA
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wire mcb3_rzq;
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wire mcb3_rzq;
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wire mcb3_zio;
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wire mcb3_zio;
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`endif
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`endif
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tri1 md_pad_io;
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tri1 md; // bi-directional phy config data
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wire mdc; // phy config clock
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wire uart0_cts;
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wire uart0_cts;
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wire uart0_rx;
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wire uart0_rx;
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wire uart0_rts;
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wire uart0_rts;
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wire uart0_tx;
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wire uart0_tx;
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wire [3:0] eth_mtxd;
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wire eth_mtxdv;
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wire eth_mtxerr;
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wire [3:0] eth_mrxd;
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wire eth_mrxdv;
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// ======================================
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// ======================================
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// Instantiate FPGA
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// Instantiate FPGA
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// ======================================
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// ======================================
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system u_system (
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system u_system (
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.mcb3_zio ( mcb3_zio ),
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.mcb3_zio ( mcb3_zio ),
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`endif
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`endif
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// Ethernet MII signals
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// Ethernet MII signals
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.mtx_clk_pad_i ( clk_25mhz ),
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.mtx_clk_pad_i ( clk_25mhz ),
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.mtxd_pad_o ( ),
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.mtxd_pad_o ( eth_mrxd ),
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.mtxen_pad_o ( ),
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.mtxen_pad_o ( eth_mrxdv ),
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.mtxerr_pad_o ( ),
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.mtxerr_pad_o ( ),
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.mrx_clk_pad_i ( clk_25mhz ),
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.mrx_clk_pad_i ( clk_25mhz ),
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.mrxd_pad_i ( 4'd0 ),
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.mrxd_pad_i ( eth_mtxd ),
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.mrxdv_pad_i ( 1'd0 ),
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.mrxdv_pad_i ( eth_mtxdv ),
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.mrxerr_pad_i ( 1'd0 ),
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.mrxerr_pad_i ( eth_mtxerr ),
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.mcoll_pad_i ( 1'd0 ),
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.mcoll_pad_i ( 1'd0 ),
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.mcrs_pad_i ( 1'd0 ), // Assert Carrier Sense from PHY
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.mcrs_pad_i ( 1'd0 ), // Assert Carrier Sense from PHY
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.phy_reset_n ( ),
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.phy_reset_n ( ),
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// Ethernet MD signals
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// Ethernet Management Data signals
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.md_pad_io ( md_pad_io ),
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.md_pad_io ( md ),
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.mdc_pad_o ( )
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.mdc_pad_o ( mdc ),
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// LEDs
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.led ( )
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);
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);
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// ======================================
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// Instantiate Ethernet Test Device
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// ======================================
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eth_test u_eth_test(
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.md_io ( md ),
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.mdc_i ( mdc ),
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.mtx_clk_i ( clk_25mhz ),
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.mtxd_o ( eth_mtxd ),
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.mtxdv_o ( eth_mtxdv ),
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.mtxerr_o ( eth_mtxerr ),
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.mrxd_i ( eth_mrxd ),
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.mrxdv_i ( eth_mrxdv )
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);
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// ======================================
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// ======================================
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// Instantiate DDR3 Memory Model
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// Instantiate DDR3 Memory Model
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// ======================================
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// ======================================
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`ifdef XILINX_FPGA
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`ifdef XILINX_FPGA
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ddr3_model_c3 #(
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ddr3_model_c3 #(
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.rst_n ( ddr3_reset_n )
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.rst_n ( ddr3_reset_n )
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);
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);
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`endif
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`endif
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// ======================================
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// ======================================
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// Instantiate Testbench UART
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// Instantiate Testbench UART
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// ======================================
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// ======================================
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tb_uart u_tb_uart (
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tb_uart u_tb_uart (
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.i_uart_cts_n ( uart0_cts ), // Clear To Send
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.i_uart_cts_n ( uart0_cts ), // Clear To Send
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.o_uart_txd ( uart0_tx )
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.o_uart_txd ( uart0_tx )
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);
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);
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// ======================================
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// ======================================
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// Global module for xilinx hardware simulations
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// Global module for xilinx hardware simulations
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// ======================================
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// ======================================
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`ifdef XILINX_FPGA
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`ifdef XILINX_FPGA
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`define GLBL
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`define GLBL
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begin
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begin
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boot_mem_file_address = hex_chars_to_32bits (aligned_line[119*8-1:111*8]);
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boot_mem_file_address = hex_chars_to_32bits (aligned_line[119*8-1:111*8]);
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boot_mem_file_data = hex_chars_to_32bits (aligned_line[110*8-1:102*8]);
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boot_mem_file_data = hex_chars_to_32bits (aligned_line[110*8-1:102*8]);
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`ifdef AMBER_A25_CORE
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`ifdef AMBER_A25_CORE
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boot_mem_file_data_128 = `U_BOOT_MEM.u_mem.mem[boot_mem_file_address[12:4]];
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boot_mem_file_data_128 = `U_BOOT_MEM.u_mem.mem[boot_mem_file_address[BOOT_MSB:4]];
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`U_BOOT_MEM.u_mem.mem[boot_mem_file_address[12:4]] =
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`U_BOOT_MEM.u_mem.mem[boot_mem_file_address[BOOT_MSB:4]] =
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insert_32_into_128 ( boot_mem_file_address[3:2],
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insert_32_into_128 ( boot_mem_file_address[3:2],
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boot_mem_file_data_128,
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boot_mem_file_data_128,
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boot_mem_file_data );
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boot_mem_file_data );
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`else
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`else
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`U_BOOT_MEM.u_mem.mem[boot_mem_file_address[12:2]] = boot_mem_file_data;
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`U_BOOT_MEM.u_mem.mem[boot_mem_file_address[BOOT_MSB:2]] = boot_mem_file_data;
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`endif
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`endif
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`ifdef AMBER_LOAD_MEM_DEBUG
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`ifdef AMBER_LOAD_MEM_DEBUG
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$display ("Load Boot Mem: PAddr: 0x%08x, Data 0x%08x",
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$display ("Load Boot Mem: PAddr: 0x%08x, Data 0x%08x",
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boot_mem_file_address, boot_mem_file_data);
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boot_mem_file_address, boot_mem_file_data);
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