//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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// //
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// //
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// Testbench UART //
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// Testbench UART //
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// //
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// //
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// This file is part of the Amber project //
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// This file is part of the Amber project //
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// http://www.opencores.org/project,amber //
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// http://www.opencores.org/project,amber //
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// //
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// //
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// Description //
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// Description //
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// Provides a target to test the wishbone UART against. //
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// Provides a target to test the wishbone UART against. //
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// //
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// //
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// Author(s): //
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// Author(s): //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// //
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// //
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//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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// //
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// //
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// Copyright (C) 2010 Authors and OPENCORES.ORG //
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// Copyright (C) 2010 Authors and OPENCORES.ORG //
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// //
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// //
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// This source file may be used and distributed without //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// the original copyright notice and the associated disclaimer. //
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// //
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// //
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// This source file is free software; you can redistribute it //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// later version. //
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// //
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// //
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// This source is distributed in the hope that it will be //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// details. //
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// //
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// //
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// You should have received a copy of the GNU Lesser General //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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// //
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//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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`timescale 1 ps / 1 ps
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`timescale 1 ps / 1 ps
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`include "system_config_defines.v"
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`include "global_defines.v"
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module tb_uart (
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module tb_uart (
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input i_uart_cts_n, // Clear To Send
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input i_uart_cts_n, // Clear To Send
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output reg o_uart_txd,
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output reg o_uart_txd,
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output o_uart_rts_n, // Request to Send
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output o_uart_rts_n, // Request to Send
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input i_uart_rxd
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input i_uart_rxd
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);
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);
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assign o_uart_rts_n = 1'd0; // allow the other side to transmit all the time
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assign o_uart_rts_n = 1'd0; // allow the other side to transmit all the time
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// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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// Baud Rate Configuration
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// Baud Rate Configuration
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// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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// Baud period in nanoseconds
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// Baud period in nanoseconds
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localparam UART_BAUD = `AMBER_UART_BAUD; // Hz
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localparam UART_BAUD = `AMBER_UART_BAUD; // Hz
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localparam UART_BIT_PERIOD = 1000000000 / UART_BAUD; // nS
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localparam UART_BIT_PERIOD = 1000000000 / UART_BAUD; // nS
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// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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reg clk_uart;
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reg clk_uart;
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reg clk_uart_rst_n;
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reg clk_uart_rst_n;
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reg [1:0] rx_state;
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reg [1:0] rx_state;
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reg [2:0] rx_bit;
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reg [2:0] rx_bit;
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reg [7:0] rx_byte;
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reg [7:0] rx_byte;
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reg [3:0] rx_tap;
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reg [3:0] rx_tap;
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reg [3:0] rx_bit_count;
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reg [3:0] rx_bit_count;
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wire rx_bit_start;
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wire rx_bit_start;
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wire rx_start_negedge;
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wire rx_start_negedge;
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reg rx_start_negedge_d1;
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reg rx_start_negedge_d1;
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reg [1:0] tx_state;
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reg [1:0] tx_state;
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reg [2:0] tx_bit;
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reg [2:0] tx_bit;
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reg [7:0] tx_byte;
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reg [7:0] tx_byte;
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reg [3:0] tx_bit_count;
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reg [3:0] tx_bit_count;
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wire tx_bit_start;
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wire tx_bit_start;
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wire tx_start;
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wire tx_start;
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wire loopback;
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wire loopback;
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wire tx_push;
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wire tx_push;
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reg tx_push_r;
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reg tx_push_r;
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wire tx_push_toggle;
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wire tx_push_toggle;
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wire [7:0] txd;
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wire [7:0] txd;
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wire txfifo_empty;
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wire txfifo_empty;
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wire txfifo_full;
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wire txfifo_full;
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reg [7:0] tx_fifo [15:0];
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reg [7:0] tx_fifo [15:0];
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reg [4:0] txfifo_wp;
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reg [4:0] txfifo_wp;
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reg [4:0] txfifo_rp;
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reg [4:0] txfifo_rp;
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// ======================================================
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// ======================================================
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// UART Clock
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// UART Clock
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// ======================================================
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// ======================================================
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// runs at 10x baud rate
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// runs at 10x baud rate
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initial
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initial
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begin
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begin
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clk_uart = 1'd0;
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clk_uart = 1'd0;
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forever #(UART_BIT_PERIOD*100/2) clk_uart = ~clk_uart;
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forever #(UART_BIT_PERIOD*100/2) clk_uart = ~clk_uart;
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end
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end
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initial
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initial
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begin
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begin
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// in reset
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// in reset
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clk_uart_rst_n = 1'd0;
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clk_uart_rst_n = 1'd0;
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// out of reset
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// out of reset
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#(UART_BIT_PERIOD*1000) clk_uart_rst_n = 1'd1;
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#(UART_BIT_PERIOD*1000) clk_uart_rst_n = 1'd1;
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end
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end
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// ======================================================
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// ======================================================
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// UART Receive
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// UART Receive
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// ======================================================
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// ======================================================
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always @( posedge clk_uart or negedge clk_uart_rst_n )
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always @( posedge clk_uart or negedge clk_uart_rst_n )
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if ( ~clk_uart_rst_n )
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if ( ~clk_uart_rst_n )
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rx_bit_count <= 'd0;
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rx_bit_count <= 'd0;
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else if ( rx_bit_count == 4'd9 )
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else if ( rx_bit_count == 4'd9 )
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rx_bit_count <= 'd0;
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rx_bit_count <= 'd0;
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// align the bit count to the centre each incoming bit
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// align the bit count to the centre each incoming bit
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else if ( rx_start_negedge )
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else if ( rx_start_negedge )
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rx_bit_count <= 'd0;
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rx_bit_count <= 'd0;
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else
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else
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rx_bit_count <= rx_bit_count + 1'd1;
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rx_bit_count <= rx_bit_count + 1'd1;
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assign rx_bit_start = rx_bit_count == 4'd0;
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assign rx_bit_start = rx_bit_count == 4'd0;
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assign rx_start_negedge = rx_tap[3] && !rx_tap[2] && rx_state == 2'd0;
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assign rx_start_negedge = rx_tap[3] && !rx_tap[2] && rx_state == 2'd0;
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always @( posedge clk_uart or negedge clk_uart_rst_n )
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always @( posedge clk_uart or negedge clk_uart_rst_n )
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if ( ~clk_uart_rst_n )
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if ( ~clk_uart_rst_n )
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begin
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begin
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rx_state <= 'd0;
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rx_state <= 'd0;
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rx_bit <= 'd0;
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rx_bit <= 'd0;
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rx_byte <= 'd0;
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rx_byte <= 'd0;
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rx_tap <= 'd0;
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rx_tap <= 'd0;
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rx_start_negedge_d1 <= 'd0;
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rx_start_negedge_d1 <= 'd0;
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end
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end
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else
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else
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begin
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begin
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rx_tap <= { rx_tap[2:0], i_uart_rxd };
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rx_tap <= { rx_tap[2:0], i_uart_rxd };
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rx_start_negedge_d1 <= rx_start_negedge;
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rx_start_negedge_d1 <= rx_start_negedge;
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if ( rx_bit_start )
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if ( rx_bit_start )
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begin
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begin
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case ( rx_state )
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case ( rx_state )
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// wait for start bit edge at end of tap
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// wait for start bit edge at end of tap
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// then sample bits at start of tap, approx
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// then sample bits at start of tap, approx
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// in the center of each bit
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// in the center of each bit
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2'd0: if ( rx_start_negedge_d1 )
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2'd0: if ( rx_start_negedge_d1 )
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rx_state <= 2'd1;
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rx_state <= 2'd1;
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// 8 bits in a word
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// 8 bits in a word
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2'd1: if ( rx_bit == 3'd7 )
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2'd1: if ( rx_bit == 3'd7 )
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rx_state <= 2'd2;
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rx_state <= 2'd2;
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// stop bit
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// stop bit
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2'd2: rx_state <= 2'd0;
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2'd2: rx_state <= 2'd0;
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endcase
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endcase
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if ( rx_state == 2'd1 )
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if ( rx_state == 2'd1 )
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begin
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begin
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rx_bit <= rx_bit + 1'd1;
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rx_bit <= rx_bit + 1'd1;
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// UART sends LSB first
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// UART sends LSB first
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rx_byte <= {i_uart_rxd, rx_byte[7:1]};
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rx_byte <= {i_uart_rxd, rx_byte[7:1]};
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end
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end
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// Ignore carriage returns so don't get a blank line
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// Ignore carriage returns so don't get a blank line
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// between every printed line in silumations
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// between every printed line in silumations
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if ( rx_state == 2'd2 && rx_byte != 8'h0d && rx_byte != 8'h0c )
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if ( rx_state == 2'd2 && rx_byte != 8'h0d && rx_byte != 8'h0c )
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$write("%c", rx_byte);
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$write("%c", rx_byte);
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end
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end
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end
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end
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// ========================================================
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// ========================================================
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// UART Transmit
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// UART Transmit
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// ========================================================
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// ========================================================
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// Get control bits from the wishbone uart test register
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// Get control bits from the wishbone uart test register
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assign tx_start = `U_TEST_MODULE.tb_uart_control_reg[0];
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assign tx_start = `U_TEST_MODULE.tb_uart_control_reg[0];
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assign loopback = `U_TEST_MODULE.tb_uart_control_reg[1];
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assign loopback = `U_TEST_MODULE.tb_uart_control_reg[1];
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always @* `U_TEST_MODULE.tb_uart_status_reg[1:0] = {txfifo_full, txfifo_empty};
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always @* `U_TEST_MODULE.tb_uart_status_reg[1:0] = {txfifo_full, txfifo_empty};
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assign tx_push = `U_TEST_MODULE.tb_uart_push;
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assign tx_push = `U_TEST_MODULE.tb_uart_push;
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assign txd = `U_TEST_MODULE.tb_uart_txd_reg;
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assign txd = `U_TEST_MODULE.tb_uart_txd_reg;
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assign tx_bit_start = tx_bit_count == 4'd0;
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assign tx_bit_start = tx_bit_count == 4'd0;
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assign txfifo_empty = txfifo_wp == txfifo_rp;
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assign txfifo_empty = txfifo_wp == txfifo_rp;
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assign txfifo_full = txfifo_wp == {~txfifo_rp[4], txfifo_rp[3:0]};
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assign txfifo_full = txfifo_wp == {~txfifo_rp[4], txfifo_rp[3:0]};
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// Detect when the tx_push signal changes value. It is on a different
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// Detect when the tx_push signal changes value. It is on a different
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// clock domain so this is needed to detect it cleanly
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// clock domain so this is needed to detect it cleanly
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always @( posedge clk_uart or negedge clk_uart_rst_n )
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always @( posedge clk_uart or negedge clk_uart_rst_n )
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if ( ~clk_uart_rst_n )
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if ( ~clk_uart_rst_n )
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tx_push_r <= 'd0;
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tx_push_r <= 'd0;
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else
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else
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tx_push_r <= tx_push;
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tx_push_r <= tx_push;
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assign tx_push_toggle = tx_push ^ tx_push_r;
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assign tx_push_toggle = tx_push ^ tx_push_r;
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always @( posedge clk_uart or negedge clk_uart_rst_n )
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always @( posedge clk_uart or negedge clk_uart_rst_n )
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if ( ~clk_uart_rst_n )
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if ( ~clk_uart_rst_n )
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tx_bit_count <= 'd0;
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tx_bit_count <= 'd0;
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else if ( tx_bit_count == 4'd9 )
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else if ( tx_bit_count == 4'd9 )
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tx_bit_count <= 'd0;
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tx_bit_count <= 'd0;
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else
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else
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tx_bit_count <= tx_bit_count + 1'd1;
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tx_bit_count <= tx_bit_count + 1'd1;
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// Transmit FIFO. 8 entries
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// Transmit FIFO. 8 entries
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always @( posedge clk_uart or negedge clk_uart_rst_n )
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always @( posedge clk_uart or negedge clk_uart_rst_n )
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if ( ~clk_uart_rst_n )
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if ( ~clk_uart_rst_n )
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begin
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begin
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txfifo_wp <= 'd0;
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txfifo_wp <= 'd0;
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end
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end
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else if ( !loopback && tx_push_toggle && !txfifo_full )
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else if ( !loopback && tx_push_toggle && !txfifo_full )
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begin
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begin
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tx_fifo[txfifo_wp[3:0]] <= txd;
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tx_fifo[txfifo_wp[3:0]] <= txd;
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txfifo_wp <= txfifo_wp + 1'd1;
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txfifo_wp <= txfifo_wp + 1'd1;
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end
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end
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else if ( !loopback && tx_push_toggle && txfifo_full )
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else if ( !loopback && tx_push_toggle && txfifo_full )
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begin
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begin
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`TB_WARNING_MESSAGE
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`TB_WARNING_MESSAGE
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$display("TB UART FIFO overflow");
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$display("TB UART FIFO overflow");
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end
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end
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// loopback received byte into tx buffer
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// loopback received byte into tx buffer
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else if ( loopback && rx_state == 2'd2 && rx_bit_start )
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else if ( loopback && rx_state == 2'd2 && rx_bit_start )
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begin
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begin
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tx_fifo[txfifo_wp[3:0]] <= rx_byte;
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tx_fifo[txfifo_wp[3:0]] <= rx_byte;
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txfifo_wp <= txfifo_wp + 1'd1;
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txfifo_wp <= txfifo_wp + 1'd1;
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end
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end
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always @( posedge clk_uart or negedge clk_uart_rst_n )
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always @( posedge clk_uart or negedge clk_uart_rst_n )
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if ( ~clk_uart_rst_n )
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if ( ~clk_uart_rst_n )
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begin
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begin
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tx_state <= 'd0;
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tx_state <= 'd0;
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tx_bit <= 'd0;
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tx_bit <= 'd0;
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tx_byte <= 'd0;
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tx_byte <= 'd0;
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o_uart_txd <= 1'd1;
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o_uart_txd <= 1'd1;
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txfifo_rp <= 'd0;
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txfifo_rp <= 'd0;
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end
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end
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else
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else
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begin
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begin
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if ( tx_bit_start )
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if ( tx_bit_start )
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begin
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begin
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case ( tx_state )
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case ( tx_state )
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// wait for trigger to start transmitting
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// wait for trigger to start transmitting
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2'd0: if ( tx_start && !txfifo_empty && !i_uart_cts_n )
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2'd0: if ( tx_start && !txfifo_empty && !i_uart_cts_n )
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begin
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begin
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tx_state <= 2'd1;
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tx_state <= 2'd1;
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tx_byte <= tx_fifo[txfifo_rp[3:0]];
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tx_byte <= tx_fifo[txfifo_rp[3:0]];
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txfifo_rp <= txfifo_rp + 1'd1;
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txfifo_rp <= txfifo_rp + 1'd1;
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// transmit start bit
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// transmit start bit
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o_uart_txd <= 1'd0;
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o_uart_txd <= 1'd0;
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end
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end
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// 8 bits in a word
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// 8 bits in a word
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2'd1: if ( !i_uart_cts_n )
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2'd1: if ( !i_uart_cts_n )
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begin
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begin
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if ( tx_bit == 3'd7 )
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if ( tx_bit == 3'd7 )
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tx_state <= 2'd2;
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tx_state <= 2'd2;
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tx_bit <= tx_bit + 1'd1;
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tx_bit <= tx_bit + 1'd1;
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tx_byte <= {1'd0, tx_byte[7:1]};
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tx_byte <= {1'd0, tx_byte[7:1]};
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// UART sends LSB first
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// UART sends LSB first
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o_uart_txd <= tx_byte[0];
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o_uart_txd <= tx_byte[0];
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end
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end
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// stop bit
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// stop bit
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2'd2: begin
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2'd2: begin
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tx_state <= 2'd0;
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tx_state <= 2'd0;
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o_uart_txd <= 1'd1;
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o_uart_txd <= 1'd1;
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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endmodule
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endmodule
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