| Line 109... |
Line 109... |
*(unsigned int *) ( ADR_ETHMAC_BDBASE + 0x200 + packet*8 ) = 0x0000e000;
|
*(unsigned int *) ( ADR_ETHMAC_BDBASE + 0x200 + packet*8 ) = 0x0000e000;
|
else
|
else
|
*(unsigned int *) ( ADR_ETHMAC_BDBASE + 0x200 + packet*8 ) = 0x0000c000;
|
*(unsigned int *) ( ADR_ETHMAC_BDBASE + 0x200 + packet*8 ) = 0x0000c000;
|
}
|
}
|
|
|
|
|
/* Enable EthMac interrupts in Ethmac core */
|
/* Enable EthMac interrupts in Ethmac core */
|
/* Receive frame and receive error botgh enabled */
|
/* Receive frame and receive error botgh enabled */
|
/* When a bad frame is received is still gets written to a buffer
|
/* When a bad frame is received is still gets written to a buffer
|
so needs to be dealt with */
|
so needs to be dealt with */
|
*(unsigned int *) ( ADR_ETHMAC_INT_MASK ) = 0xc;
|
*(unsigned int *) ( ADR_ETHMAC_INT_MASK ) = 0xc;
|
| Line 174... |
Line 175... |
int addr;
|
int addr;
|
int bmcr;
|
int bmcr;
|
int stat;
|
int stat;
|
int phy_id;
|
int phy_id;
|
int link_up = 1;
|
int link_up = 1;
|
|
|
time_t* link_timer;
|
time_t* link_timer;
|
|
|
link_timer = init_timer();
|
link_timer = init_timer();
|
|
|
/* Bring PHY out of reset */
|
/* Bring PHY out of reset */
|
| Line 191... |
Line 191... |
stat = mdio_read(phy_id, MII_BMSR);
|
stat = mdio_read(phy_id, MII_BMSR);
|
stat = mdio_read(phy_id, MII_BMSR);
|
stat = mdio_read(phy_id, MII_BMSR);
|
if(!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
|
if(!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
|
break;
|
break;
|
}
|
}
|
|
/* Failed to find a PHY on the md bus */
|
|
if (addr == 32)
|
|
return 0;
|
|
|
/* Reset PHY */
|
/* Reset PHY */
|
bmcr = mdio_read(phy_id, MII_BMCR);
|
bmcr = mdio_read(phy_id, MII_BMCR);
|
mdio_write(phy_id, MII_BMCR, bmcr | BMCR_RESET);
|
mdio_write(phy_id, MII_BMCR, bmcr | BMCR_RESET);
|
|
|
| Line 207... |
Line 210... |
bmcr = mdio_read(phy_id, MII_BMCR);
|
bmcr = mdio_read(phy_id, MII_BMCR);
|
mdio_write(phy_id, MII_BMCR, bmcr | BMCR_ANRESTART);
|
mdio_write(phy_id, MII_BMCR, bmcr | BMCR_ANRESTART);
|
|
|
/* Wait for link up */
|
/* Wait for link up */
|
/* Print PHY status MII_BMSR = Basic Mode Status Register*/
|
/* Print PHY status MII_BMSR = Basic Mode Status Register*/
|
/* allow 2 seconds for the link to come up before giving up */
|
/* allow a few seconds for the link to come up before giving up */
|
set_timer(link_timer, 5000);
|
set_timer(link_timer, 5000);
|
|
|
while (!((stat = mdio_read(phy_id, MII_BMSR)) & BMSR_LSTATUS)) {
|
while (!((stat = mdio_read(phy_id, MII_BMSR)) & BMSR_LSTATUS)) {
|
if (timer_expired(link_timer)) {
|
if (timer_expired(link_timer)) {
|
link_up = 0;
|
link_up = 0;
|
break;
|
break;
|
}
|
}
|
| Line 291... |
Line 295... |
/* Mask ethmac interrupts */
|
/* Mask ethmac interrupts */
|
*(volatile unsigned int *) ( ADR_ETHMAC_INT_MASK ) = 0;
|
*(volatile unsigned int *) ( ADR_ETHMAC_INT_MASK ) = 0;
|
|
|
int_src = *(volatile unsigned int *) ( ADR_ETHMAC_INT_SOURCE );
|
int_src = *(volatile unsigned int *) ( ADR_ETHMAC_INT_SOURCE );
|
|
|
|
if (int_src) {
|
for (buffer=0; buffer<ETHMAC_RX_BUFFERS; buffer++) {
|
for (buffer=0; buffer<ETHMAC_RX_BUFFERS; buffer++) {
|
|
|
rx_buf_status = *(volatile unsigned int *) ( ADR_ETHMAC_BDBASE + 0x200 + buffer*8 );
|
rx_buf_status = *(volatile unsigned int *) ( ADR_ETHMAC_BDBASE + 0x200 + buffer*8 );
|
|
|
if ((rx_buf_status & 0x8000) == 0) {
|
if ((rx_buf_status & 0x8000) == 0) {
|
| Line 306... |
Line 311... |
*(unsigned int *) ( ADR_ETHMAC_BDBASE + 0x200 + buffer*8 ) = 0x0000e000;
|
*(unsigned int *) ( ADR_ETHMAC_BDBASE + 0x200 + buffer*8 ) = 0x0000e000;
|
else
|
else
|
*(unsigned int *) ( ADR_ETHMAC_BDBASE + 0x200 + buffer*8 ) = 0x0000c000;
|
*(unsigned int *) ( ADR_ETHMAC_BDBASE + 0x200 + buffer*8 ) = 0x0000c000;
|
}
|
}
|
}
|
}
|
|
}
|
|
|
/* Clear all ethmac interrupts */
|
/* Clear all ethmac interrupts */
|
*(volatile unsigned int *) ( ADR_ETHMAC_INT_SOURCE ) = int_src;
|
*(volatile unsigned int *) ( ADR_ETHMAC_INT_SOURCE ) = int_src;
|
|
|
/* UnMask ethmac interrupts */
|
/* UnMask ethmac interrupts */
|
