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https://opencores.org/ocsvn/aor3000/aor3000/trunk
[/] [aor3000/] [trunk/] [README.md] - Diff between revs 2 and 3
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- the aoR3000 core;
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- the aoR3000 core;
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- an Altera JTAG UART;
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- an Altera JTAG UART;
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- an Altera SDRAM controller;
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- an Altera SDRAM controller;
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- a simple time interrupt device;
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- a simple time interrupt device;
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- onchip memory for the boot code of the aoR3000;
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- onchip memory for the boot code of the aoR3000;
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- a Altera JTAG to Avalon Master Bridge to upload the Linux kernel;
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- an Altera JTAG to Avalon Master Bridge to upload the Linux kernel;
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The SoC is designed for the Terasic DE2-115 board.
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The SoC is designed for the Terasic DE2-115 board.
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To compile the SoC the following steps have to be taken:
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To compile the SoC the following steps have to be taken:
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- open the Altera Quartus II project in syn/soc/;
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- open the Altera Quartus II project in syn/soc/;
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