Subversion Repositories apbtoaes128

        begin: IV_BKP_MUX

        begin: IV_BKP_MUX

                integer i;

                integer i;

                iv_mux_out  = {32{1'b0}};

                iv_mux_out  = {32{1'b0}};

                bkp_mux_out = {32{1'b0}};

                bkp_mux_out = {32{1'b0}};

                for(i = 0; i < 4; i = i + 1)

                for(i = 0; i < 4; i = i + 1)

                                if(col_en[i] | iv_sel_rd[i])

                                if(col_en[i] | iv_sel_rd[i])

                                        begin

                                        begin

                                                iv_mux_out  = iv[i];

                                                iv_mux_out  = iv[i];

                                                bkp_mux_out = bkp[i];

                                                bkp_mux_out = bkp[i];

                                        end

                                        end

// IV and BKP Registers

// IV and BKP Registers

generate

generate

        genvar l;

        genvar l;

        for(l = 0; l < 4;l=l+1)

        for(l = 0; l < 4;l=l+1)

                always @(posedge clk, negedge rst_n)

                always @(posedge clk, negedge rst_n)

                begin

                begin

                                if(!rst_n)

                                if(!rst_n)

                                begin

                                begin

                                                iv[l]    <= {32{1'b0}};

                                                iv[l]    <= {32{1'b0}};

// Columns Definition

// Columns Definition

generate

generate

        genvar i;

        genvar i;

        for(i = 0; i < 4; i = i + 1)

        for(i = 0; i < 4; i = i + 1)

                always @(posedge clk, negedge rst_n)

                always @(posedge clk, negedge rst_n)

                        begin

                        begin

                                if(!rst_n)

                                if(!rst_n)

                                        col[3 - i] <= {32{1'b0}};

                                        col[3 - i] <= {32{1'b0}};

                                else

                                else

                                if(col_en[3 - i])

                                if(col_en[3 - i])

                                        col[3 - i] <= col_in[32*(i + 1) - 1 : 32*i];

                                        col[3 - i] <= col_in[32*(i + 1) - 1 : 32*i];

                        end

                        end

endgenerate

endgenerate

// Shift Rows Operation

// Shift Rows Operation

assign sr_input_3 = (enc_dec) ? add_rk_out : col[3];

assign sr_input_3 = (enc_dec) ? add_rk_out : col[3];

assign sr_input_0 = (enc_dec) ? col[0] : add_rk_out;

assign sr_input_0 = (enc_dec) ? col[0] : add_rk_out;

// Key registers

// Key registers

generate

generate

        genvar j;

        genvar j;

        for(j = 0; j < 4; j = j + 1)

        for(j = 0; j < 4; j = j + 1)

                always @(posedge clk, negedge rst_n)

                always @(posedge clk, negedge rst_n)

                        begin

                        begin

                                if(!rst_n)

                                if(!rst_n)

                                        begin

                                        begin

                                                key_host[3 - j] <= {32{1'b0}};

                                                key_host[3 - j] <= {32{1'b0}};

                                                if(key_en_sel[3 - j] || key_init || key_host_en[3 - j])

                                                if(key_en_sel[3 - j] || key_init || key_host_en[3 - j])

                                                        key[3 - j] <= (key_sel_mux) ? key_out[32*(j + 1) - 1 : 32*j] : ( (key_host_en[3 - j]) ? bus_in : key_host[3 - j] );

                                                        key[3 - j] <= (key_sel_mux) ? key_out[32*(j + 1) - 1 : 32*j] : ( (key_host_en[3 - j]) ? bus_in : key_host[3 - j] );

                                        end

                                        end

                        end

                        end

endgenerate

endgenerate

assign key_in = {key[0], key[1], key[2], key[3]};

assign key_in = {key[0], key[1], key[2], key[3]};

assign key1_mux_cnt = bypass_key_en & enc_dec;

assign key1_mux_cnt = bypass_key_en & enc_dec;