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[/] [artificial_neural_network/] [trunk/] [ANN_kernel/] [RTL_VHDL_files/] [activation_function.vhd] - Diff between revs 3 and 8

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`entity activation_function is`	`entity activation_function is`
`generic`	`generic`
`(`	`(`
	`lsbit : natural := 10;`
`f_type : string := "linear"; -- Activation function type`	`f_type : string := "linear"; -- Activation function type`
`Nbit : natural := 8 -- Bit width`	`Nbit : natural := 8 -- Bit width`
`);`	`);`
`port`	`port`
`(`	`(`
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`);`	`);`
`end activation_function;`	`end activation_function;`

`architecture Structural of activation_function is`	`architecture Structural of activation_function is`

	`component af_sigmoid is`
	`generic`
	`(`
	`Nbit : natural := 8`
	`);`
	`port`
	`(`
	`reset : in std_logic;`
	`clk : in std_logic;`
	`run_in : in std_logic; -- Start and input data validation`
	`inputs : in std_logic_vector(Nbit-1 downto 0); -- Input data`
	`run_out : out std_logic; -- Output data validation, run_in for the next layer`
	`outputs : out std_logic_vector(Nbit-1 downto 0) -- Output data`
	`);`
	`end component;`

`begin`	`begin`

`-- Linear activation function. It is a direct assignment:`	`-- Linear activation function. It is a direct assignment:`
`linear_f:`	`linear_f:`
`if (f_type = "linear") generate`	`if (f_type = "linear") generate`
Line 51...	Line 68...
`end generate;`	`end generate;`

`-- Example 1: sigmoid activation function implemented as a Look-Up-Table (LUT):`	`-- Example 1: sigmoid activation function implemented as a Look-Up-Table (LUT):`
`Sigmoid_f:`	`Sigmoid_f:`
`if (f_type = "siglut") generate`	`if (f_type = "siglut") generate`
`siglut_inst: entity work.af_sigmoid`	`siglut_inst: af_sigmoid`
`generic map`	`generic map`
`(`	`(`
`Nbit => Nbit`	`Nbit => Nbit`
`)`	`)`
`port map`	`port map`
Line 73...	Line 90...
`Sigmoid2_f:`	`Sigmoid2_f:`
`if (f_type = "siglu2") generate`	`if (f_type = "siglu2") generate`
`siglut_inst: entity work.af_sigmoid2`	`siglut_inst: entity work.af_sigmoid2`
`generic map`	`generic map`
`(`	`(`
`Nbit => Nbit`	`Nbit => Nbit,`
	`lsbit => lsbit`
`)`	`)`
`port map`	`port map`
`(`	`(`
`reset => reset,`	`reset => reset,`
`clk => clk,`	`clk => clk,`

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[/] [artificial_neural_network/] [trunk/] [ANN_kernel/] [RTL_VHDL_files/] [activation_function.vhd] - Diff between revs 3 and 8