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https://opencores.org/ocsvn/artificial_neural_network/artificial_neural_network/trunk
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Line 44... |
);
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);
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end adder_tree;
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end adder_tree;
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architecture Behavioral of adder_tree is
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architecture Behavioral of adder_tree is
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component adder_tree is
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generic
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(
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NumIn : integer := 9; -- Number of inputs
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Nbit : integer := 12 -- Bit width of the input data
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);
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port
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(
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-- Input ports
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reset : in std_logic;
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clk : in std_logic;
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en : in std_logic; -- Enable
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inputs : in std_logic_vector((Nbit*NumIn)-1 downto 0); -- Input data
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-- Output ports
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en_out : out std_logic; -- Output enable (output data validation)
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output : out std_logic_vector(Nbit-1 downto 0) -- Output of the tree adder
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);
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end component;
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constant NumIn2 : integer := NumIn/2; -- Number of imputs of the next adder tree layer
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constant NumIn2 : integer := NumIn/2; -- Number of imputs of the next adder tree layer
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signal next_en : std_logic := '0'; -- Next adder tree layer enable
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signal next_en : std_logic := '0'; -- Next adder tree layer enable
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signal res : std_logic_vector((Nbit*((NumIn2)+(NumIn mod 2)))-1 downto 0); -- Partial results
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signal res : std_logic_vector((Nbit*((NumIn2)+(NumIn mod 2)))-1 downto 0); -- Partial results
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end process;
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end process;
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recursion:
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recursion:
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if (NumIn > 2) generate
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if (NumIn > 2) generate
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sub_adder_tree: entity work.adder_tree
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sub_adder_tree: adder_tree
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generic map
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generic map
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(
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(
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NumIn => (NumIn2)+(NumIn mod 2),
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NumIn => (NumIn2)+(NumIn mod 2),
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Nbit => Nbit
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Nbit => Nbit
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)
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)
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