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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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library work;
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use work.wb_init.all; -- initialization package, comment out when not used
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-- Deprecated XPS library:
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-- Deprecated XPS library:
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--library proc_common_v3_00_a;
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--library proc_common_v3_00_a;
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--use proc_common_v3_00_a.proc_common_pkg.all; -- Only for simulation ( pad_power2() )
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--use proc_common_v3_00_a.proc_common_pkg.all; -- Only for simulation ( pad_power2() )
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entity layerSP_top is
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entity layerSP_top is
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generic
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generic
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(
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(
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NumN : natural := 8; ------- Number of neurons of the layer
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WBinit : boolean := false;
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NumIn : natural := 64; ------- Number of inputs of each neuron
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LNum : natural := 0; ------- layer number (needed for initialization)
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NumN : natural := 34; ------- Number of neurons of the layer
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NumIn : natural := 27; ------- Number of inputs of each neuron
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NbitIn : natural := 8; ------- Bit width of the input data
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NbitIn : natural := 8; ------- Bit width of the input data
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NbitW : natural := 8; ------- Bit width of weights and biases
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NbitW : natural := 32; ------- Bit width of weights and biases
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NbitOut : natural := 12; ------- Bit width of the output data
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NbitOut : natural := 8; ------- Bit width of the output data
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lra_l : natural := 10; ------- Layer RAM address length. It should value log2(NumN)+log2(NumIn)
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lra_l : natural := 11; ------- Layer RAM address length. It should value log2(NumN)+log2(NumIn)
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wra_l : natural := 6; ------- Weight RAM address length. It should value log2(NumIn)
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wra_l : natural := 5; ------- Weight RAM address length. It should value log2(NumIn)
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bra_l : natural := 3; ------- Bias RAM address length. It should value log2(NumN)
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bra_l : natural := 6; ------- Bias RAM address length. It should value log2(NumN)
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LSbit : natural := 4 ------- Less significant bit of the outputs
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LSbit : natural := 6 ------- Less significant bit of the outputs
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);
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);
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port
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port
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(
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(
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-- Input ports
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-- Input ports
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end layerSP_top;
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end layerSP_top;
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architecture Behavioral of layerSP_top is
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architecture Behavioral of layerSP_top is
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--type ramd_type is array (pad_power2(NumIn)-1 downto 0) of std_logic_vector(NbitW-1 downto 0); -- Optimal: 32 or 64 spaces
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--type layer_ram is array (pad_power2(NumN)-1 downto 0) of ramd_type;
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type ramd_type is array (NumIn-1 downto 0) of std_logic_vector(NbitW-1 downto 0); -- Optimal: 32 or 64 spaces
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type ramd_type is array (NumIn-1 downto 0) of std_logic_vector(NbitW-1 downto 0); -- Optimal: 32 or 64 spaces
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type layer_ram is array (NumN-1 downto 0) of ramd_type;
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type layer_ram is array (NumN-1 downto 0) of ramd_type;
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type outm_type is array (NumN-1 downto 0) of std_logic_vector(NbitW-1 downto 0);
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type outm_type is array (NumN-1 downto 0) of std_logic_vector(NbitW-1 downto 0);
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signal lram : layer_ram; -- Layer RAM. One RAM per neuron. It stores the weights
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signal breg : outm_type; -- Bias registers. They can not be RAM because they are accessed simultaneously
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function fw_init(LNum : natural) return layer_ram is
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variable tmp_arr : layer_ram := (others => (others => (others => '0'))) ;
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begin
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if WBinit = true then
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for i in 0 to NumIn-1 loop
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for j in 0 to NumN-1 loop
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tmp_arr(j)(i) := w_init(LNum)(i)(j);
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end loop;
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end loop;
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end if;
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return tmp_arr ;
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end fw_init;
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function fb_init(LNum : natural) return outm_type is
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variable tmp_arr : outm_type := (others => (others => '0')) ;
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begin
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if WBinit = true then
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for i in 0 to NumN-1 loop
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tmp_arr(i) := b_init(LNum)(i);
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end loop;
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end if;
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return tmp_arr;
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end fb_init;
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signal lram : layer_ram := fw_init(LNum); -- Layer RAM. One RAM per neuron. It stores the weights
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signal breg : outm_type := fb_init(LNum); -- Bias registers. They can not be RAM because they are accessed simultaneously
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signal outm : outm_type; -- RAM outputs to be multiplexed into rdata
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signal outm : outm_type; -- RAM outputs to be multiplexed into rdata
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signal m_sel : std_logic_vector(NumN-1 downto 0); -------- RAM select
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signal m_sel : std_logic_vector(NumN-1 downto 0); -------- RAM select
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signal Wyb : std_logic_vector((NbitW*NumN)-1 downto 0); --- Weight vectors
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signal Wyb : std_logic_vector((NbitW*NumN)-1 downto 0); --- Weight vectors
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signal bias : std_logic_vector((NbitW*NumN)-1 downto 0); --- Bias vector
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signal bias : std_logic_vector((NbitW*NumN)-1 downto 0); --- Bias vector
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signal Nouts : std_logic_vector((NbitOut*NumN)-1 downto 0); -- Outputs from neurons
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signal Nouts : std_logic_vector((NbitOut*NumN)-1 downto 0); -- Outputs from neurons
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else
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else
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Wyb((NbitW*(i+1))-1 downto NbitW*i) <= lram(i)(cont);
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Wyb((NbitW*(i+1))-1 downto NbitW*i) <= lram(i)(cont);
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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outm(i) <= lram(i)(to_integer(uaddr(wra_l-1 downto 0))); -- Read all RAM
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outm(i) <= lram(i)(to_integer(uaddr(wra_l-1 downto 0))) when (uaddr(wra_l-1 downto 0) <= NumIn-1) else
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(others => '0') ; -- Read all RAM
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-- In my case I have 27 inputs and 34 neurons in the first layer. When I address
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-- the 1 layer's inputs for the second neuron the layer which acccepts a 6 bit wide
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-- input address (layer 2) sees the ..1 00100 (34) number and interprets it as an input
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-- address (which goes only up to 33) hence the bound check failure
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-- fix: I've changed the assignment to a conditional one to check if we are not
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-- trying to read a weight of an input higher than the number of this layer's inputs.
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end generate;
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end generate;
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-- Synchronous read including breg:
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-- Synchronous read including breg:
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process (clk)
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process (clk)
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begin
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begin
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if (clk'event and clk = '1') then
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if (clk'event and clk = '1') then
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--report "addr: " & integer'image(wra_l-1);
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--report "addr: " & integer'image(to_integer(uaddr(wra_l-1 downto 0)) );
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if (m_en = '1') then
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if (m_en = '1') then
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if (b_sel = '1') then
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if (b_sel = '1') then
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rdata <= breg(to_integer(uaddr(bra_l-1 downto 0))); -- Bias registers selected
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rdata <= breg(to_integer(uaddr(bra_l-1 downto 0))); -- Bias registers selected
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else -- Other RAM selected:
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else -- Other RAM selected:
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rdata <= outm(to_integer(uaddr(lra_l-1 downto wra_l))); -- Multiplexes RAM outputs
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rdata <= outm(to_integer(uaddr(lra_l-1 downto wra_l))); -- Multiplexes RAM outputs
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cont <= 0; -- Restarts input counter
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cont <= 0; -- Restarts input counter
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aux2_en3 <= '1';
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aux2_en3 <= '1';
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else
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else
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cont <= cont +1;
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cont <= cont +1;
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end if;
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end if;
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--elsif (cont = NumIn-1) then -- for layers with more that
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-- cont <= 0; -- 1 neuron uncommenting this
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-- aux2_en3 <= '1'; -- solved a problem with cont resetting
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end if;
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end if;
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en2 <= en1;
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en2 <= en1;
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if (cont = 0 and run_in = '1') then
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if (cont = 0 and run_in = '1') then
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aux_a0 <= '1'; -- At the count beginning
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aux_a0 <= '1'; -- At the count beginning
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else
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else
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