////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////
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//// Author: ////
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//// Author: ////
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//// - Balaji V. Iyer, bviyer@ncsu.edu ////
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//// - Balaji V. Iyer, bviyer@ncsu.edu ////
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////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`include "timescale.v"
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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module tb_or1200_wbmux();
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module tb_or1200_wbmux();
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reg clk;
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reg clk;
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reg rst;
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reg rst;
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reg wb_freeze;
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reg wb_freeze;
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reg[`OR1200_RFWBOP_WIDTH-1:0] rfwb_op;
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reg[`OR1200_RFWBOP_WIDTH-1:0] rfwb_op;
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reg[`OR1200_RFWBOP_WIDTH-1:0] rfwb_op2;
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reg[`OR1200_RFWBOP_WIDTH-1:0] rfwb_op2;
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reg[31:0] muxin_a;
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reg[31:0] muxin_a;
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reg[31:0] muxin_b;
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reg[31:0] muxin_b;
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reg[31:0] muxin_c;
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reg[31:0] muxin_c;
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reg[31:0] muxin_d;
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reg[31:0] muxin_d;
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reg[31:0] muxin_a2;
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reg[31:0] muxin_a2;
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reg[31:0] muxin_b2;
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reg[31:0] muxin_b2;
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reg[31:0] muxin_c2;
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reg[31:0] muxin_c2;
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reg[31:0] muxin_d2;
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reg[31:0] muxin_d2;
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wire[31:0] muxout;
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wire[31:0] muxout;
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wire[31:0] muxout2;
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wire[31:0] muxout2;
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wire[31:0] muxreg;
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wire[31:0] muxreg;
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wire[31:0] muxreg2;
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wire[31:0] muxreg2;
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wire muxreg_valid;
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wire muxreg_valid;
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wire muxreg2_valid;
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wire muxreg2_valid;
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or1200_wbmux or1200_wbmux(.clk(clk), .rst(rst), .wb_freeze(wb_freeze),
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or1200_wbmux or1200_wbmux(.clk(clk), .rst(rst), .wb_freeze(wb_freeze),
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.rfwb_op(rfwb_op), .rfwb_op2(rfwb_op2), .muxin_a(muxin_a), .muxin_b(muxin_b),
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.rfwb_op(rfwb_op), .rfwb_op2(rfwb_op2), .muxin_a(muxin_a), .muxin_b(muxin_b),
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.muxin_c(muxin_c), .muxin_d(muxin_d), .muxin_a2(muxin_a2),.muxin_b2(muxin_b2),
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.muxin_c(muxin_c), .muxin_d(muxin_d), .muxin_a2(muxin_a2),.muxin_b2(muxin_b2),
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.muxin_c2(muxin_c2), .muxin_d2(muxin_d2), .muxout(muxout), .muxout2(muxout2),
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.muxin_c2(muxin_c2), .muxin_d2(muxin_d2), .muxout(muxout), .muxout2(muxout2),
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.muxreg(muxreg), .muxreg2(muxreg2), .muxreg_valid(muxreg_valid),
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.muxreg(muxreg), .muxreg2(muxreg2), .muxreg_valid(muxreg_valid),
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.muxreg2_valid(muxreg2_valid));
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.muxreg2_valid(muxreg2_valid));
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initial begin
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initial begin
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#0 rst=0;
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#0 rst=0;
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clk=0;
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clk=0;
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#10 rst=1;
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#10 rst=1;
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#10 rst=0;
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#10 rst=0;
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wb_freeze=0;
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wb_freeze=0;
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rfwb_op=3'b1;
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rfwb_op=3'b1;
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rfwb_op2=3'd3;
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rfwb_op2=3'd3;
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muxin_a=32'h12345678;
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muxin_a=32'h12345678;
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muxin_b=32'h23456789;
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muxin_b=32'h23456789;
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muxin_c=32'h34567890;
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muxin_c=32'h34567890;
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muxin_d=32'h4567890A;
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muxin_d=32'h4567890A;
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muxin_a2=32'h90ABCDEF;
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muxin_a2=32'h90ABCDEF;
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muxin_b2=32'h0ABCDEF9;
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muxin_b2=32'h0ABCDEF9;
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muxin_c2=32'hABCDEF90;
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muxin_c2=32'hABCDEF90;
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muxin_d2=32'hBCDEF90A;
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muxin_d2=32'hBCDEF90A;
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#10 rfwb_op=3'd3;
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#10 rfwb_op=3'd3;
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rfwb_op2=3'd5;
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rfwb_op2=3'd5;
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#10 rfwb_op=3'd5;
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#10 rfwb_op=3'd5;
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rfwb_op2=3'd7;
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rfwb_op2=3'd7;
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#10 rfwb_op=3'd7;
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#10 rfwb_op=3'd7;
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rfwb_op2=3'd1;
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rfwb_op2=3'd1;
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end
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end
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always #5 clk = ~clk;
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always #5 clk = ~clk;
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endmodule
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endmodule
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