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library verilog;

library verilog;

use verilog.vl_types.all;

use verilog.vl_types.all;

entity or1200_sb_fifo is

entity or1200_sb_fifo is

    generic(

    generic(

        dw              : integer := 68;

        dw              : integer := 68;

        fw              : integer := 2;

        fw              : integer := 2;

        fl              : integer := 4

        fl              : integer := 4

    );

    );

    port(

    port(

        clk_i           : in     vl_logic;

        clk_i           : in     vl_logic;

        rst_i           : in     vl_logic;

        rst_i           : in     vl_logic;

        dat_i           : in     vl_logic_vector;

        dat_i           : in     vl_logic_vector;

        wr_i            : in     vl_logic;

        wr_i            : in     vl_logic;

        rd_i            : in     vl_logic;

        rd_i            : in     vl_logic;

        dat_o           : out    vl_logic_vector;

        dat_o           : out    vl_logic_vector;

        full_o          : out    vl_logic;

        full_o          : out    vl_logic;

        empty_o         : out    vl_logic

        empty_o         : out    vl_logic

    );

    );

end or1200_sb_fifo;

end or1200_sb_fifo;