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library verilog;

library verilog;

use verilog.vl_types.all;

use verilog.vl_types.all;

entity or1200_spram_64x24 is

entity or1200_spram_64x24 is

    generic(

    generic(

        aw              : integer := 6;

        aw              : integer := 6;

        dw              : integer := 24

        dw              : integer := 24

    );

    );

    port(

    port(

        clk             : in     vl_logic;

        clk             : in     vl_logic;

        rst             : in     vl_logic;

        rst             : in     vl_logic;

        ce              : in     vl_logic;

        ce              : in     vl_logic;

        we              : in     vl_logic;

        we              : in     vl_logic;

        oe              : in     vl_logic;

        oe              : in     vl_logic;

        addr            : in     vl_logic_vector;

        addr            : in     vl_logic_vector;

        di              : in     vl_logic_vector;

        di              : in     vl_logic_vector;

        do              : out    vl_logic_vector

        do              : out    vl_logic_vector

    );

    );

end or1200_spram_64x24;

end or1200_spram_64x24;