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Line 15... |
signal System_Clock_In_N : std_logic;
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signal System_Clock_In_N : std_logic;
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signal GTREFCLK_IN_P : std_logic;
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signal GTREFCLK_IN_P : std_logic;
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signal GTREFCLK_IN_N : std_logic;
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signal GTREFCLK_IN_N : std_logic;
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signal USER_CLK_IN_P : std_logic;
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signal USER_CLK_IN_N : std_logic;
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signal USER_SMA_CLK_OUT_P : std_logic;
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signal USER_SMA_CLK_OUT_N : std_logic;
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signal TX_Out_P : std_logic;
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signal TX_Out_P : std_logic;
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signal TX_Out_N : std_logic;
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signal TX_Out_N : std_logic;
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signal RX_In_P : std_logic;
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signal RX_In_P : std_logic;
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signal RX_In_N : std_logic;
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signal RX_In_N : std_logic;
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signal Lock_Out : std_logic;
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signal valid_out : std_logic;
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signal valid_out : std_logic;
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begin
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begin
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RX_In_N <= TX_Out_N;
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RX_In_N <= TX_Out_N;
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RX_In_P <= TX_Out_P;
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RX_In_P <= TX_Out_P;
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uut : entity work.Interface_Test
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uut : entity work.Interface_Test
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port map (
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port map (
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System_Clock_In_P => System_Clock_In_P,
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System_Clock_In_P => System_Clock_In_P,
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System_Clock_In_N => System_Clock_In_N,
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System_Clock_In_N => System_Clock_In_N,
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GTREFCLK_IN_P => GTREFCLK_IN_P,
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GTREFCLK_IN_P => GTREFCLK_IN_P,
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GTREFCLK_IN_N => GTREFCLK_IN_N,
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GTREFCLK_IN_N => GTREFCLK_IN_N,
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USER_CLK_IN_P => USER_CLK_IN_P,
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USER_CLK_IN_N => USER_CLK_IN_N,
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USER_SMA_CLK_OUT_P => USER_SMA_CLK_OUT_P,
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USER_SMA_CLK_OUT_N => USER_SMA_CLK_OUT_N,
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RX_In_N => RX_In_N,
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RX_In_N => RX_In_N,
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RX_In_P => RX_In_P,
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RX_In_P => RX_In_P,
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TX_Out_N => TX_Out_N,
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TX_Out_N => TX_Out_N,
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TX_Out_P => TX_Out_P,
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TX_Out_P => TX_Out_P,
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Lock_Out => Lock_Out,
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valid_out => valid_out
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valid_out => valid_out
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);
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);
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process
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process
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begin
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begin
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