library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
|
|
entity testbench_decoder is
|
entity testbench_decoder is
|
end entity testbench_decoder;
|
end entity testbench_decoder;
|
|
|
architecture tb_decoder of testbench_decoder is
|
architecture tb_decoder of testbench_decoder is
|
|
|
signal Clk : std_logic; -- Clock input
|
signal Clk : std_logic; -- Clock input
|
signal Reset : std_logic; -- Reset decoder
|
signal Reset : std_logic; -- Reset decoder
|
signal Data_In : std_logic_vector(66 downto 0); -- Data input
|
signal Data_In : std_logic_vector(66 downto 0); -- Data input
|
signal Decoder_En : std_logic; -- Enables the decoder
|
signal Decoder_En : std_logic; -- Enables the decoder
|
signal Data_Valid_In : std_logic;
|
signal Data_Valid_In : std_logic;
|
signal Data_Valid_Out : std_logic;
|
signal Data_Valid_Out : std_logic;
|
signal Data_Out : std_logic_vector(63 downto 0);-- Decoded 64-bit output
|
signal Data_Out : std_logic_vector(63 downto 0);-- Decoded 64-bit output
|
signal Data_Control : std_logic; -- Indicates whether the word is data or control
|
signal Data_Control : std_logic; -- Indicates whether the word is data or control
|
|
|
signal Sync_Locked : std_logic;
|
signal Sync_Locked : std_logic;
|
signal Sync_Error : std_logic;
|
signal Sync_Error : std_logic;
|
signal Bitslip : std_logic;
|
signal Bitslip : std_logic;
|
|
|
constant CLK_PERIOD : time := 10 ns;
|
constant CLK_PERIOD : time := 10 ns;
|
|
|
begin
|
begin
|
uut : entity work.decoder
|
uut : entity work.decoder
|
port map (
|
port map (
|
clk => clk,
|
clk => clk,
|
reset => reset,
|
reset => reset,
|
Decoder_En => Decoder_En,
|
Decoder_En => Decoder_En,
|
|
|
Data_in => Data_in,
|
Data_in => Data_in,
|
Data_out => Data_out,
|
Data_out => Data_out,
|
Data_Valid_In => Data_Valid_In,
|
Data_Valid_In => Data_Valid_In,
|
Data_Valid_Out => Data_Valid_Out,
|
Data_Valid_Out => Data_Valid_Out,
|
Data_control => Data_control,
|
Data_control => Data_control,
|
|
|
Sync_Locked => Sync_locked,
|
Sync_Locked => Sync_locked,
|
Sync_error => Sync_error,
|
Sync_error => Sync_error,
|
Bitslip => Bitslip
|
Bitslip => Bitslip
|
|
|
);
|
);
|
|
|
Clk_process :process
|
Clk_process :process
|
begin
|
begin
|
clk <= '1';
|
clk <= '1';
|
wait for CLK_PERIOD/2; --for half of clock period clk stays at '0'.
|
wait for CLK_PERIOD/2; --for half of clock period clk stays at '0'.
|
clk <= '0';
|
clk <= '0';
|
wait for CLK_PERIOD/2; --for next half of clock period clk stays at '1'.
|
wait for CLK_PERIOD/2; --for next half of clock period clk stays at '1'.
|
end process;
|
end process;
|
|
|
simulation : process
|
simulation : process
|
begin
|
begin
|
wait for 1 ps;
|
wait for 1 ps;
|
decoder_en <= '1';
|
decoder_en <= '1';
|
reset <= '1';
|
reset <= '1';
|
data_in <= (others=>'0');
|
data_in <= (others=>'0');
|
|
|
wait for CLK_PERIOD;
|
wait for CLK_PERIOD;
|
|
|
wait for CLK_PERIOD;
|
wait for CLK_PERIOD;
|
|
|
reset <= '0';
|
reset <= '0';
|
Data_in <= "101" & X"1f5e5d5c5b5a5958";
|
Data_in <= "101" & X"1f5e5d5c5b5a5958";
|
wait for CLK_PERIOD;
|
wait for CLK_PERIOD;
|
|
|
|
|
Data_in <= "101" & X"2f5e5d5c5b5a5958";
|
Data_in <= "101" & X"2f5e5d5c5b5a5958";
|
wait for CLK_PERIOD;
|
wait for CLK_PERIOD;
|
|
|
|
|
data_in <= "101" & X"3f5e5d5c5b5a5958";
|
data_in <= "101" & X"3f5e5d5c5b5a5958";
|
wait for CLK_PERIOD;
|
wait for CLK_PERIOD;
|
|
|
|
|
Data_in <= "101" & X"4f21a2a3a4a5a6a7";
|
Data_in <= "101" & X"4f21a2a3a4a5a6a7";
|
wait for CLK_PERIOD;
|
wait for CLK_PERIOD;
|
|
|
|
|
data_in <= "101" & X"5f5e5a5c5b60f2a0";
|
data_in <= "101" & X"5f5e5a5c5b60f2a0";
|
wait for CLK_PERIOD;
|
wait for CLK_PERIOD;
|
|
|
data_in <= "001" & X"635e22a3a4a5a7a7";
|
data_in <= "001" & X"635e22a3a4a5a7a7";
|
wait for CLK_PERIOD;
|
wait for CLK_PERIOD;
|
|
|
data_in <= "101" & X"70000FFF000000F0";
|
data_in <= "101" & X"70000FFF000000F0";
|
wait for CLK_PERIOD*2;
|
wait for CLK_PERIOD*2;
|
|
|
|
|
Data_in <= "101" & X"2f5e5d5c5b5a5958";
|
Data_in <= "101" & X"2f5e5d5c5b5a5958";
|
wait for CLK_PERIOD;
|
wait for CLK_PERIOD;
|
|
|
wait for CLK_PERIOD;
|
wait for CLK_PERIOD;
|
|
|
|
|
data_in <= "110" & X"8050505050050505";
|
data_in <= "110" & X"8050505050050505";
|
wait for CLK_PERIOD*3;
|
wait for CLK_PERIOD*3;
|
|
|
data_in <= "101" & X"9486576758050505";
|
data_in <= "101" & X"9486576758050505";
|
wait for CLK_PERIOD;
|
wait for CLK_PERIOD;
|
|
|
|
|
data_in <= "101" & X"60b35d5dc4a582a7";
|
data_in <= "101" & X"60b35d5dc4a582a7";
|
wait for CLK_PERIOD;
|
wait for CLK_PERIOD;
|
|
|
|
|
data_in <= "101" & X"2f5e5d5c5b5a5958";
|
data_in <= "101" & X"2f5e5d5c5b5a5958";
|
wait for CLK_PERIOD*12;
|
wait for CLK_PERIOD*12;
|
|
|
data_in <= "111" & X"2f5e5d5c5b5a5958";
|
data_in <= "111" & X"2f5e5d5c5b5a5958";
|
wait for CLK_PERIOD;
|
wait for CLK_PERIOD;
|
|
|
Data_in <= "101" & X"1f5e5d5c5b5a5958";
|
Data_in <= "101" & X"1f5e5d5c5b5a5958";
|
wait for CLK_PERIOD;
|
wait for CLK_PERIOD;
|
|
|
|
|
Data_in <= "101" & X"2f5e5d5c5b5a5958";
|
Data_in <= "101" & X"2f5e5d5c5b5a5958";
|
wait for CLK_PERIOD;
|
wait for CLK_PERIOD;
|
|
|
|
|
data_in <= "101" & X"3f5e5d5c5b5a5958";
|
data_in <= "101" & X"3f5e5d5c5b5a5958";
|
wait for CLK_PERIOD;
|
wait for CLK_PERIOD;
|
|
|
|
|
Data_in <= "101" & X"4f21a2a3a4a5a6a7";
|
Data_in <= "101" & X"4f21a2a3a4a5a6a7";
|
wait for CLK_PERIOD;
|
wait for CLK_PERIOD;
|
|
|
|
|
data_in <= "101" & X"5f5e5a5c5b60f2a0";
|
data_in <= "101" & X"5f5e5a5c5b60f2a0";
|
wait for CLK_PERIOD;
|
wait for CLK_PERIOD;
|
|
|
data_in <= "001" & X"635e22a3a4a5a7a7";
|
data_in <= "001" & X"635e22a3a4a5a7a7";
|
wait for CLK_PERIOD;
|
wait for CLK_PERIOD;
|
|
|
data_in <= "101" & X"5f5e5a5c5b60f2a0";
|
data_in <= "101" & X"5f5e5a5c5b60f2a0";
|
wait for CLK_PERIOD;
|
wait for CLK_PERIOD;
|
|
|
data_in <= "001" & X"635e22a3a4a5a7a7";
|
data_in <= "001" & X"635e22a3a4a5a7a7";
|
wait for CLK_PERIOD;
|
wait for CLK_PERIOD;
|
|
|
data_in <= "101" & X"70000FFF000000F0";
|
data_in <= "101" & X"70000FFF000000F0";
|
wait for CLK_PERIOD*2;
|
wait for CLK_PERIOD*2;
|
|
|
|
|
Data_in <= "101" & X"2f5e5d5c5b5a5958";
|
Data_in <= "101" & X"2f5e5d5c5b5a5958";
|
wait for CLK_PERIOD;
|
wait for CLK_PERIOD;
|
|
|
data_in <= "110" & X"8050505050050505";
|
data_in <= "110" & X"8050505050050505";
|
wait for CLK_PERIOD*3;
|
wait for CLK_PERIOD*3;
|
|
|
data_in <= "101" & X"9486576758050505";
|
data_in <= "101" & X"9486576758050505";
|
wait for CLK_PERIOD;
|
wait for CLK_PERIOD;
|
|
|
data_in <= "101" & X"60b35d5dc4a582a7";
|
data_in <= "101" & X"60b35d5dc4a582a7";
|
wait for CLK_PERIOD*60;
|
wait for CLK_PERIOD*60;
|
|
|
data_in <= "110" & X"8050505050050505";
|
data_in <= "110" & X"8050505050050505";
|
wait for CLK_PERIOD*3;
|
wait for CLK_PERIOD*3;
|
|
|
data_in <= "101" & X"9486576758050505";
|
data_in <= "101" & X"9486576758050505";
|
wait for CLK_PERIOD;
|
wait for CLK_PERIOD;
|
|
|
|
|
data_in <= "101" & X"60b35d5dc4a582a7";
|
data_in <= "101" & X"60b35d5dc4a582a7";
|
wait for CLK_PERIOD;
|
wait for CLK_PERIOD;
|
|
|
|
|
data_in <= "101" & X"2f5e5d5c5b5a5958";
|
data_in <= "101" & X"2f5e5d5c5b5a5958";
|
wait for CLK_PERIOD*12;
|
wait for CLK_PERIOD*12;
|
|
|
data_in <= "111" & X"2c8e5d5c5b5a5958";
|
data_in <= "111" & X"2c8e5d5c5b5a5958";
|
wait for CLK_PERIOD;
|
wait for CLK_PERIOD;
|
|
|
Data_in <= "101" & X"1f5e5d5c5b5a5958";
|
Data_in <= "101" & X"1f5e5d5c5b5a5958";
|
wait for CLK_PERIOD*26;
|
wait for CLK_PERIOD*26;
|
|
|
data_in <= "111" & X"2c8e5d5c5b5a5958";
|
data_in <= "111" & X"2c8e5d5c5b5a5958";
|
wait for CLK_PERIOD*18;
|
wait for CLK_PERIOD*18;
|
|
|
data_in <= "101" & X"1f5e5d5c5b5a5958";
|
data_in <= "101" & X"1f5e5d5c5b5a5958";
|
wait for CLK_PERIOD;
|
wait for CLK_PERIOD;
|
wait;
|
wait;
|
end process;
|
end process;
|
|
|
end architecture tb_decoder;
|
end architecture tb_decoder;
|
|
|
|
|
