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entity testbench_burst is
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entity testbench_burst is
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end entity testbench_burst;
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end entity testbench_burst;
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architecture tb_burst of testbench_burst is
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architecture tb_burst of testbench_burst is
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--for uut : CRC use entity work.CRC(error_check);
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constant BurstMax : positive := 64; --256
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constant BurstMax : positive := 64; --256
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constant BurstShort : positive := 32; --512 - 256 - 128 - 64 - 32
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constant BurstShort : positive := 32; --512 - 256 - 128 - 64 - 32
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signal clk : std_logic; -- System clock
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signal clk : std_logic; -- System clock
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signal reset : std_logic; -- Reset, use for initialization.
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signal reset : std_logic; -- Reset, use for initialization.
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signal Data_in : std_logic_vector(63 downto 0); -- Input data
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signal Data_in : std_logic_vector(63 downto 0); -- Input data
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signal Data_out : std_logic_vector(63 downto 0); -- To scrambling/framing
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signal Data_out : std_logic_vector(63 downto 0); -- To scrambling/framing
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signal Data_valid_out : std_logic; -- Indicate data transmitted is valid
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signal Data_valid_out : std_logic; -- Indicate data transmitted is valid
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signal Data_control_out : std_logic; -- Control word indication
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signal Data_control_out : std_logic; -- Control word indication
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--signal CRC24_TX : std_logic_vector(63 downto 0); -- Data to CRC-24
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--signal CRC24_Cal : std_logic_vector(63 downto 0); -- Calculated CRC-24
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--signal CRC24_En : std_logic; -- Indicate the CRC-24 the data is valid
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signal FIFO_meta : std_logic;
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signal FIFO_meta : std_logic;
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signal FIFO_read : std_logic; -- Request data from the FIFO
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signal FIFO_read : std_logic; -- Request data from the FIFO
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signal FIFO_data : std_logic_vector(9 downto 0); -- Determines how many bytes have to be transmitted
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signal FIFO_data : std_logic_vector(9 downto 0); -- Determines how many bytes have to be transmitted
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constant CLK_PERIOD : time := 10 ns;
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constant CLK_PERIOD : time := 10 ns;
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begin
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begin
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uut : entity work.burst
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uut : entity work.Burst_Framer
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generic map(
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generic map(
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BurstShort => BurstShort,
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BurstShort => BurstShort,
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BurstMax => BurstMax
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BurstMax => BurstMax
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)
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)
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port map (
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port map (
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Line 49... |
TX_Channel => TX_Channel,
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TX_Channel => TX_Channel,
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Data_in => Data_in,
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Data_in => Data_in,
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Data_out => Data_out,
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Data_out => Data_out,
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Data_valid_out => Data_valid_out,
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Data_valid_out => Data_valid_out,
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Data_control_out => Data_control_out,
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Data_control_out => Data_control_out,
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--CRC24_TX => CRC24_TX,
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--CRC24_Cal => CRC24_Cal,
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--CRC24_En => CRC24_En,
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FIFO_read => FIFO_read,
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FIFO_read => FIFO_read,
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FIFO_meta => FIFO_meta,
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FIFO_meta => FIFO_meta,
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FIFO_data => FIFO_data
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FIFO_data => FIFO_data
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);
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);
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