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[/] [core1990_interlaken/] [trunk/] [gateware/] [simulation/] [framing_meta_tb.vhd] - Diff between revs 6 and 9

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Rev 6 Rev 9
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
 
 
entity testbench_meta is
entity testbench_meta is
end entity testbench_meta;
end entity testbench_meta;
 
 
architecture tb_meta of testbench_meta is
architecture tb_meta of testbench_meta is
 
    signal clk   : std_logic;
signal clk                              : std_logic;                                -- System clock
    signal reset : std_logic;
signal reset                    : std_logic;                                -- Reset, use for initialization.
 
 
 
signal TX_Enable : std_logic;
signal TX_Enable : std_logic;
signal HealthLane : std_logic := '0';
 
signal HealthInterface : std_logic := '0';
 
 
 
signal Data_in : std_logic_vector(63 downto 0);         -- Input data
    signal HealthLane       : std_logic;                      -- Lane status bit transmitted in diagnostic
signal Data_out : std_logic_vector(63 downto 0);       -- To scrambling/framing
    signal HealthInterface  : std_logic;                      -- Interface status bit transmitted in diagnostic
signal Data_valid_in : std_logic;                                               -- Indicate data transmitted is valid
 
signal Data_valid_out : std_logic;                                              -- Indicate data transmitted is valid
 
signal Data_Control_In  : std_logic;
 
signal Data_control_out : std_logic;                   -- Control word indication
 
 
 
signal Gearboxready : std_logic;
    signal Data_In          : std_logic_vector(63 downto 0);  -- Input data
 
    signal Data_Out         : std_logic_vector(63 downto 0); -- To scrambling/framing
 
    signal Data_Valid_In    : std_logic;                                      -- Indicate data received is valid
 
    signal Data_Valid_Out   : std_logic;                                      -- Indicate data transmitted is valid
 
    signal Data_Control_In  : std_logic;                      -- Control word indication from the burst component
 
    signal Data_Control_Out : std_logic;                     -- Control word indication
 
 
signal FIFO_read : std_logic;                                           -- Request data from the FIFO
    signal Gearboxready : std_logic;
 
    signal FIFO_read    : std_logic;
 
 
constant CLK_PERIOD : time := 10 ns;
    constant CLK_PERIOD : time := 10 ns;
 
 
begin
begin
  uut : entity work.metaframing
    uut : entity work.Meta_Framer
  port map (
  port map (
    clk => clk,
        clk => clk,
    reset => reset,
    reset => reset,
 
 
    TX_Enable => TX_Enable,
    TX_Enable => TX_Enable,
 
 
    HealthLane => HealthLane,
    HealthLane => HealthLane,
    HealthInterface => HealthInterface,
    HealthInterface => HealthInterface,
 
 
    Data_in => Data_in,
    Data_in => Data_in,
    Data_out => Data_out,
        Data_out => Data_out,
    Data_valid_in => Data_valid_in,
        Data_valid_in => Data_valid_in,
    Data_valid_out => Data_valid_out,
        Data_valid_out => Data_valid_out,
    Data_control_in => Data_control_in,
        Data_control_in => Data_control_in,
    Data_control_out => Data_control_out,
    Data_control_out => Data_control_out,
 
 
    Gearboxready => Gearboxready,
    Gearboxready => Gearboxready,
    FIFO_read => FIFO_read
        FIFO_read => FIFO_read
  );
    );
 
 
   Clk_process :process
    Clk_process :process
     begin
    begin
          clk <= '1';
        clk <= '1';
          wait for CLK_PERIOD/2;  --for half of clock period clk stays at '0'.
        wait for CLK_PERIOD/2;  --for half of clock period clk stays at '0'.
          clk <= '0';
        clk <= '0';
          wait for CLK_PERIOD/2;  --for next half of clock period clk stays at '1'.
        wait for CLK_PERIOD/2;  --for next half of clock period clk stays at '1'.
     end process;
    end process;
 
 
    simulation : process
    simulation : process
    begin
    begin
       wait for 1 ps;
        wait for 1 ps;
 
 
       reset <= '1';
        reset <= '1';
       data_in <= (others=>'0');
        data_in <= (others=>'0');
 
 
       wait for CLK_PERIOD;
        wait for CLK_PERIOD;
 
 
       wait for CLK_PERIOD;
        wait for CLK_PERIOD;
 
 
       Gearboxready <= '1';
        Gearboxready <= '1';
       reset <= '0';
        reset <= '0';
       TX_Enable <= '1';
        TX_Enable <= '1';
       Data_valid_in <= '1';
        Data_valid_in <= '1';
       Data_in <= X"1f5e5d5c5b5a5958";
        Data_in <= X"1f5e5d5c5b5a5958";
       wait for CLK_PERIOD;
        wait for CLK_PERIOD;
 
 
 
 
       Data_in <= X"2f5e5d5c5b5a5958";
        Data_in <= X"2f5e5d5c5b5a5958";
       wait for CLK_PERIOD;
        wait for CLK_PERIOD;
 
 
 
 
       data_in <= X"3f5e5d5c5b5a5958";
        data_in <= X"3f5e5d5c5b5a5958";
       wait for CLK_PERIOD;
        wait for CLK_PERIOD;
 
 
       Data_in <= X"4f21a2a3a4a5a6a7";
        Data_in <= X"4f21a2a3a4a5a6a7";
       wait for CLK_PERIOD;
        wait for CLK_PERIOD;
 
 
 
 
       data_in <= X"5f5e5a5c5b60f2a0";
        data_in <= X"5f5e5a5c5b60f2a0";
       wait for CLK_PERIOD;
        wait for CLK_PERIOD;
 
 
       data_in  <= X"635e22a3a4a5a7a7";
        data_in  <= X"635e22a3a4a5a7a7";
       wait for CLK_PERIOD;
        wait for CLK_PERIOD;
 
 
       data_in  <= X"70000FFF000000F0";
        data_in  <= X"70000FFF000000F0";
       wait for CLK_PERIOD*2;
        wait for CLK_PERIOD*2;
 
 
       Data_in <= X"2f5e5d5c5b5a5958";
        Data_in <= X"2f5e5d5c5b5a5958";
       wait for CLK_PERIOD;
        wait for CLK_PERIOD;
 
 
       Gearboxready <= '0';
        Gearboxready <= '0';
       data_in  <= X"8050505050050505";
        data_in  <= X"8050505050050505";
       wait for CLK_PERIOD*2;
        wait for CLK_PERIOD*2;
 
 
       Gearboxready <= '1';
        Gearboxready <= '1';
       data_in  <= X"9486576758050505";
        data_in  <= X"9486576758050505";
       wait for CLK_PERIOD;
        wait for CLK_PERIOD;
 
 
       data_in <= X"60b35d5dc4a582a7";
        data_in <= X"60b35d5dc4a582a7";
       wait for CLK_PERIOD;
        wait for CLK_PERIOD;
 
 
       data_in <= X"2f5e5d5c5b5a5958";
        data_in <= X"2f5e5d5c5b5a5958";
       wait for CLK_PERIOD;
        wait for CLK_PERIOD;
 
 
       data_in <= X"5f5e5a5c5b60f2a0";
        data_in <= X"5f5e5a5c5b60f2a0";
       wait for CLK_PERIOD;
        wait for CLK_PERIOD;
 
 
       data_in  <= X"635e22a3a4a5a7a7";
        data_in  <= X"635e22a3a4a5a7a7";
       wait for CLK_PERIOD;
        wait for CLK_PERIOD;
 
 
       data_in  <= X"70000FFF000000F0";
        data_in  <= X"70000FFF000000F0";
       wait for CLK_PERIOD*2;
        wait for CLK_PERIOD*2;
 
 
       Data_in <= X"2f5e5d5c5b5a5958";
        Data_in <= X"2f5e5d5c5b5a5958";
       wait for CLK_PERIOD;
        wait for CLK_PERIOD;
 
 
       data_in  <= X"8050505050050505";
        data_in  <= X"8050505050050505";
       wait for CLK_PERIOD*3;
        wait for CLK_PERIOD*3;
 
 
       data_in  <= X"9486576758050505";
        data_in  <= X"9486576758050505";
       wait for CLK_PERIOD;
        wait for CLK_PERIOD;
 
 
       data_in <= X"60b35d5dc4a582a7";
        data_in <= X"60b35d5dc4a582a7";
       wait for CLK_PERIOD;
        wait for CLK_PERIOD;
 
 
       data_in <= X"5f5e5a5c5b60f2a0";
        data_in <= X"5f5e5a5c5b60f2a0";
        wait for CLK_PERIOD;
        wait for CLK_PERIOD;
 
 
        data_in  <= X"635e22a3a4a5a7a7";
        data_in  <= X"635e22a3a4a5a7a7";
        wait for CLK_PERIOD;
        wait for CLK_PERIOD;
 
 
        data_in  <= X"70000FFF000000F0";
        data_in  <= X"70000FFF000000F0";
        wait for CLK_PERIOD*2;
        wait for CLK_PERIOD*2;
 
 
        Data_in <= X"2f5e5d5c5b5a5958";
        Data_in <= X"2f5e5d5c5b5a5958";
        wait for CLK_PERIOD;
        wait for CLK_PERIOD;
 
 
        data_in  <= X"8050505050050505";
        data_in  <= X"8050505050050505";
 
 
       wait;
        wait;
    end process;
    end process;
 
 
end architecture tb_meta;
end architecture tb_meta;
 
 
 
 

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