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--
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-- This file is an automatically generated VHDL testbench
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-- by MakeTestBench (version 1.702)
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--
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-- Created on : 01 March 2018
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--
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-- Tested entity : interlaken_scrambler
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-- Tested entity from : scrambler_interlaken.vhd
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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entity testbench_scrambler is
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entity testbench_scrambler is
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end entity testbench_scrambler;
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end entity testbench_scrambler;
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architecture tb_interlaken_scrambler of testbench_scrambler is
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architecture tb_interlaken_scrambler of testbench_scrambler is
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component Scrambler is
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port (
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clk : in std_logic;
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Scram_Rst : in std_logic;
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lane_number : in std_logic_vector(3 downto 0);
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Data_Control_In : in std_logic;
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Data_Control_Out: out std_logic;
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data_in : in std_logic_vector(63 downto 0);
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scram_en : in std_logic;
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data_out : out std_logic_vector(63 downto 0);
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Data_Valid_Out : out std_logic
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);
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end component Scrambler;
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for uut : Scrambler use entity work.Scrambler(behavior);
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signal Clk : std_logic := '1'; -- System clock
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signal Scram_Rst : std_logic := '1'; -- Scrambler reset, use for initialization
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signal Data_In : std_logic_vector (63 downto 0);-- Data input
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signal Data_Out : std_logic_vector (63 downto 0);-- Data output
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signal clk : std_logic := '1';
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signal Lane_Number : std_logic_vector (3 downto 0); -- Each lane number starts with different scrambler word
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signal Scram_Rst : std_logic := '1';
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signal Scrambler_En : std_logic; -- Input valid
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signal lane_number : std_logic_vector(3 downto 0) := "0001";
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signal Data_Control_In : std_logic; -- Indicates a control word
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signal Data_Control_In : std_logic;
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signal Data_Control_Out : std_logic; -- Output control word indication
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signal Data_Control_Out : std_logic;
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signal data_in : std_logic_vector(63 downto 0);
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signal Data_Valid_In : std_logic; -- Input valid
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signal scram_en : std_logic := '0';
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signal Data_Valid_Out : std_logic; -- Output valid
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signal data_out : std_logic_vector(63 downto 0);
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signal Gearboxready : std_logic;
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signal Data_Valid_Out : std_logic := '0';
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constant CLK_PERIOD : time := 10 ns;
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constant CLK_PERIOD : time := 10 ns;
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begin
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begin
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uut : Scrambler port map (
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uut : entity work.Scrambler
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port map (
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clk => clk,
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clk => clk,
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Scram_Rst => Scram_Rst,
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Scram_Rst => Scram_Rst,
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lane_number => lane_number,
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lane_number => lane_number,
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Data_Control_In => Data_Control_In,
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Data_Control_In => Data_Control_In,
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Data_Control_Out => Data_Control_Out,
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Data_Control_Out => Data_Control_Out,
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end process;
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end process;
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simulation : process
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simulation : process
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begin
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begin
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wait for 1 ps;
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wait for 1 ps;
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Data_Valid_Out <= '0';
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Lane_number <= "0001";
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data_in <= (others=>'0');
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data_in <= (others=>'0');
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wait for CLK_PERIOD;
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wait for CLK_PERIOD*2;
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wait for CLK_PERIOD;
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Scram_Rst <= '0';
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Scram_Rst <= '0';
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scram_en <= '1';
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scram_en <= '1';
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data_in <= X"5f5e5d5c5b5a5958";
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data_in <= X"5f5e5d5c5b5a5958";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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