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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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-- Company: Carnegie Mellon University, Pittsburgh PA
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-- Company: Eastern Washington University, Cheney, WA
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-- Engineer: Justin Wagner
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-- Engineer: Justin Wagner
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--
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--
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-- Create Date: 7/Oct/2011
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-- Create Date: 7/Oct/2011
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-- Design Name:
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-- Design Name:
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-- Module Name: arp_responder - rtl
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-- Module Name: arp_responder - rtl
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-- Project Name:
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-- Project Name:
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-- Target Devices: n/a
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-- Target Devices: n/a
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-- Tool versions:
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-- Tool versions:
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-- Description: Project for Job application to XR Trading
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--
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--
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-- Dependencies: arp_package.vhdl (Definitions of various constants)
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-- Dependencies: arp_package.vhdl (Definitions of various constants)
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--
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--
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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--the following declares the various states for the machine
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--the following declares the various states for the machine
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type state_type is (IDLE,
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type state_type is (IDLE,
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CHECK_DA, CHECK_SA, CHECK_E_TYPE, CHECK_H_TYPE, CHECK_P_TYPE,
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CHECK_DA, CHECK_SA, CHECK_E_TYPE, CHECK_H_TYPE, CHECK_P_TYPE,
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CHECK_H_LEN, CHECK_P_LEN, CHECK_OPER, CHECK_SHA, CHECK_SPA,
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CHECK_H_LEN, CHECK_P_LEN, CHECK_OPER, CHECK_SHA, CHECK_SPA,
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CHECK_THA, CHECK_TPA,
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IGNORE_THA, CHECK_TPA,
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GEN_DA, GEN_SA, GEN_E_TYPE, GEN_H_TYPE, GEN_P_TYPE,
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GEN_DA, GEN_SA, GEN_E_TYPE, GEN_H_TYPE, GEN_P_TYPE,
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GEN_H_LEN, GEN_P_LEN, GEN_OPER, GEN_SHA, GEN_SPA,
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GEN_H_LEN, GEN_P_LEN, GEN_OPER, GEN_SHA, GEN_SPA,
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GEN_THA, GEN_TPA);
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GEN_THA, GEN_TPA);
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signal SA_mem, next_SA_mem : HA_mem_type;
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signal SA_mem, next_SA_mem : HA_mem_type;
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signal SPA_mem, next_SPA_mem : PA_mem_type;
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signal SPA_mem, next_SPA_mem : PA_mem_type;
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signal next_state, state : state_type;
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signal next_state, state : state_type;
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signal next_counter, counter : std_logic_vector(3 downto 0);
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signal next_counter, counter : std_logic_vector(3 downto 0);
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signal posedge_DATA_VALID_RX : std_logic;
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signal posedge_DATA_VALID_RX : std_logic;
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signal next_DATA_VALID_TX : std_logic;
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signal next_DATA_VALID_TX, next_2_DATA_VALID_TX : std_logic;
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signal next_DATA_TX : std_logic_vector(7 downto 0);
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signal next_DATA_TX, next_2_DATA_TX : std_logic_vector(7 downto 0);
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begin
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begin
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-- A positive edge detector for the DATA_VALID_RX signal
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-- A positive edge detector for the DATA_VALID_RX signal
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ed_1: edge_detector
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ed_1: edge_detector
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-- Lets store the SPA so we can respond to it later
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-- Lets store the SPA so we can respond to it later
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next_counter <= counter + 1;
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next_counter <= counter + 1;
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next_state <= CHECK_SPA;
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next_state <= CHECK_SPA;
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next_SPA_mem(conv_integer(counter)) <= DATA_RX;
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next_SPA_mem(conv_integer(counter)) <= DATA_RX;
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if (counter >= 3) then
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if (counter >= 3) then
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next_state <= CHECK_THA;
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next_state <= IGNORE_THA;
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next_counter <= (others => '0');
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next_counter <= (others => '0');
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end if;
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end if;
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when CHECK_THA =>
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when IGNORE_THA =>
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-- Make sure we are the destination Hardware Address
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-- Ignore the destination Hardware Address (ARP requests can't fill this out by definition)
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next_state <= IGNORE_THA;
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next_counter <= counter + 1;
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next_counter <= counter + 1;
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if (DATA_RX = MY_MAC((47-(conv_integer(counter)*8)) downto (40-(conv_integer(counter)*8)))) then
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next_state <= CHECK_THA;
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if (counter >= 5) then
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if (counter >= 5) then
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next_state <= CHECK_TPA;
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next_state <= CHECK_TPA;
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next_counter <= (others => '0');
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next_counter <= (others => '0');
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end if;
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end if;
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else
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next_state <= IDLE;
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next_counter <= (others => '0');
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end if;
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when CHECK_TPA =>
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when CHECK_TPA =>
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-- Make sure we are the destination Protocol Address
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-- Make sure we are the destination Protocol Address
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next_counter <= counter + 1;
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next_counter <= counter + 1;
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if (DATA_RX = MY_IPV4((31-(conv_integer(counter)*8)) downto (24-(conv_integer(counter)*8)))) then
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if (DATA_RX = MY_IPV4((31-(conv_integer(counter)*8)) downto (24-(conv_integer(counter)*8)))) then
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begin
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begin
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if (ARESET='1') then --resetting the board
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if (ARESET='1') then --resetting the board
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DATA_VALID_TX <= '0';
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DATA_VALID_TX <= '0';
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DATA_TX <= (others => '0');
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DATA_TX <= (others => '0');
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next_2_DATA_VALID_TX <= '0';
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next_2_DATA_TX <= (others => '0');
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-- move next state values into registers on clock edge
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-- move next state values into registers on clock edge
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elsif (CLK_TX'event and CLK_TX ='1') then
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elsif (CLK_TX'event and CLK_TX ='1') then
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DATA_VALID_TX <= next_DATA_VALID_TX;
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next_2_DATA_VALID_TX <= next_DATA_VALID_TX;
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DATA_TX <= next_DATA_TX;
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next_2_DATA_TX <= next_DATA_TX;
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DATA_VALID_TX <= next_2_DATA_VALID_TX;
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DATA_TX <= next_2_DATA_TX;
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else
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else
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NULL;
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NULL;
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end if;
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end if;
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end process seq_TX;
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end process seq_TX;
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