| Line 4... |
Line 4... |
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File : fifo_srl_uni.vhd
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-- File : fifo_srl_uni.vhd
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-- Author : Tomasz Turek <tomasz.turek@gmail.com>
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-- Author : Tomasz Turek <tomasz.turek@gmail.com>
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-- Company : SzuWar INC
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-- Company : SzuWar INC
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-- Created : 13:27:31 14-03-2010
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-- Created : 13:27:31 14-03-2010
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-- Last update: 12:03:49 18-03-2010
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-- Last update: 23:23:38 20-03-2010
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-- Platform : Xilinx ISE 10.1.03
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-- Platform : Xilinx ISE 10.1.03
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-- Standard : VHDL'93
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-- Standard : VHDL'93
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Description:
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-- Description:
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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| Line 125... |
Line 125... |
signal t_mux_in : type_data_path;
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signal t_mux_in : type_data_path;
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signal t_srl_in : type_srl_path;
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signal t_srl_in : type_srl_path;
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signal t_mux_out : type_out_reg;
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signal t_mux_out : type_out_reg;
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signal t_reg_in : type_in_reg;
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signal t_reg_in : type_in_reg;
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signal one_delay : std_logic := '0';
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signal one_delay : std_logic := '0';
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signal dupa : std_logic := '0';
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signal ce_master : std_logic;
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signal full_capacity : std_logic;
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signal data_valid_off : std_logic;
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|
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begin -- architecture fifo_srl_uni_r
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begin -- architecture fifo_srl_uni_r
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v_zeros <= (others => '0');
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v_zeros <= (others => '0');
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v_ones <= (others => '1');
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v_ones <= (others => '1');
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-------------------------------------------------------------------------------
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-- Input Register --
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-------------------------------------------------------------------------------
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GR0: if iInputReg = 0 generate
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GR0: if iInputReg = 0 generate
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t_srl_in(0) <= DATA_I;
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t_srl_in(0) <= DATA_I;
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v_WRITE_ENABLE(0) <= WRITE_ENABLE_I;
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v_WRITE_ENABLE(0) <= WRITE_ENABLE_I;
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| Line 178... |
Line 181... |
end if;
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end if;
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end process P1;
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end process P1;
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end generate GR2;
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end generate GR2;
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-------------------------------------------------------------------------------
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-- Input Register --
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- FIFO Core, SRL16E based --
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-------------------------------------------------------------------------------
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G1: for i in 0 to c_srl_count - 1 generate
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G1: for i in 0 to c_srl_count - 1 generate
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G0: for j in 0 to iDataWidth - 1 generate
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G0: for j in 0 to iDataWidth - 1 generate
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SRLC16_inst : SRLC16E
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SRLC16_inst : SRLC16E
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| Line 192... |
Line 201... |
Q15 => t_srl_in(i+1)(j), -- Carry output (connect to next SRL)
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Q15 => t_srl_in(i+1)(j), -- Carry output (connect to next SRL)
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A0 => v_delay_counter(0), -- Select[0] input
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A0 => v_delay_counter(0), -- Select[0] input
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A1 => v_delay_counter(1), -- Select[1] input
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A1 => v_delay_counter(1), -- Select[1] input
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A2 => v_delay_counter(2), -- Select[2] input
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A2 => v_delay_counter(2), -- Select[2] input
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A3 => v_delay_counter(3), -- Select[3] input
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A3 => v_delay_counter(3), -- Select[3] input
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CE => v_WRITE_ENABLE(0), -- Clock enable input
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CE => ce_master, -- Clock enable input
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CLK => CLK_I, -- Clock input
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CLK => CLK_I, -- Clock input
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D => t_srl_in(i)(j) -- SRL data input
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D => t_srl_in(i)(j) -- SRL data input
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);
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);
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end generate G0;
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end generate G0;
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end generate G1;
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end generate G1;
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-------------------------------------------------------------------------------
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-- FIFO Core, SRL16E based --
|
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-------------------------------------------------------------------------------
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i_srl_select <= conv_integer((v_delay_counter(iSizeDelayCounter - 1 downto 4)));
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i_srl_select <= conv_integer((v_delay_counter(iSizeDelayCounter - 1 downto 4)));
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i_size_counter <= conv_integer(v_size_counter);
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i_size_counter <= conv_integer(v_size_counter);
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ce_master <= v_WRITE_ENABLE(0) and (not full_capacity);
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P0: process (CLK_I) is
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P0: process (CLK_I) is
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begin -- process P0
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begin -- process P0
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|
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if rising_edge(CLK_I) then
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if rising_edge(CLK_I) then
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if (v_WRITE_ENABLE(0) = '1') and (READ_ENABLE_I = '0') and (v_size_counter /= v_ones) then
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if (v_WRITE_ENABLE(0) = '1') and (READ_ENABLE_I = '0') and (i_size_counter < ififoWidth) then
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|
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if one_delay = '1' then
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if one_delay = '1' then
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v_delay_counter <= v_delay_counter + 1;
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v_delay_counter <= v_delay_counter + 1;
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one_delay <= '1';
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one_delay <= '1';
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| Line 225... |
Line 238... |
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end if;
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end if;
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v_size_counter <= v_size_counter + 1;
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v_size_counter <= v_size_counter + 1;
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|
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elsif (v_WRITE_ENABLE(0) = '0') and (READ_ENABLE_I = '1') and (v_size_counter /= v_zeros) then
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elsif (v_WRITE_ENABLE(0) = '0') and (READ_ENABLE_I = '1') and (i_size_counter > 0) then
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|
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if v_delay_counter = v_zeros then
|
if v_delay_counter = v_zeros then
|
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one_delay <= '0';
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one_delay <= '0';
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| Line 248... |
Line 261... |
v_size_counter <= v_size_counter;
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v_size_counter <= v_size_counter;
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one_delay <= one_delay;
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one_delay <= one_delay;
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|
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end if;
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end if;
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|
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if i_size_counter = 0 then
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data_valid_off <= '1';
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else
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data_valid_off <= '0';
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|
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end if;
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|
|
end if;
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end if;
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|
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end process P0;
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end process P0;
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|
|
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full_capacity <= '0' when i_size_counter < ififoWidth else '1';
|
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-------------------------------------------------------------------------------
|
|
-- Output Register --
|
|
-------------------------------------------------------------------------------
|
t_mux_out(0) <= t_mux_in(i_srl_select);
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t_mux_out(0) <= t_mux_in(i_srl_select);
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READ_VALID_O <= v_READ_ENABLE(0);
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READ_VALID_O <= v_READ_ENABLE(0) and (not data_valid_off);
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FIFO_COUNT_O <= v_size_counter;
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FIFO_COUNT_O <= v_size_counter;
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|
|
|
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GM0: if iOutputReg = 0 generate
|
GM0: if iOutputReg = 0 generate
|
|
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DATA_O <= t_mux_out(0);
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DATA_O <= t_mux_out(0);
|
v_READ_ENABLE(0) <= READ_ENABLE_I;
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v_READ_ENABLE(0) <= READ_ENABLE_I;
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|
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| Line 301... |
Line 329... |
end if;
|
end if;
|
|
|
end process P2;
|
end process P2;
|
|
|
end generate GM2;
|
end generate GM2;
|
|
-------------------------------------------------------------------------------
|
|
-- Output Register --
|
|
-------------------------------------------------------------------------------
|
|
|
PF: process (CLK_I) is
|
-------------------------------------------------------------------------------
|
begin -- process PF
|
-- Flag Generators --
|
|
-------------------------------------------------------------------------------
|
if rising_edge(CLK_I) then
|
EMPTY_FLAG_O <= '0' when (i_size_counter)> iEmptyFlagOfSet else '1';
|
|
FULL_FLAG_O <= '1' when i_size_counter >= ififoWidth - iFullFlagOfSet else '0';
|
if i_size_counter >= ififoWidth - iFullFlagOfSet then
|
-------------------------------------------------------------------------------
|
|
-- Flag Generators --
|
FULL_FLAG_O <= '1';
|
-------------------------------------------------------------------------------
|
|
|
else
|
|
|
|
FULL_FLAG_O <= '0';
|
|
|
|
end if;
|
|
|
|
if i_size_counter < iEmptyFlagOfSet then
|
|
|
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EMPTY_FLAG_O <= '1';
|
|
|
|
else
|
|
|
|
EMPTY_FLAG_O <= '0';
|
|
|
|
end if;
|
|
|
|
end if;
|
|
|
|
end process PF;
|
|
|
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|
|
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end architecture fifo_srl_uni_rtl;
|
end architecture fifo_srl_uni_rtl;
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No newline at end of file
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No newline at end of file
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