| Line 4... |
Line 4... |
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- File : tb_fifo_srl_uni_1.vhd
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-- File : tb_fifo_srl_uni_1.vhd
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-- Author : Tomasz Turek <tomasz.turek@gmail.com>
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-- Author : Tomasz Turek <tomasz.turek@gmail.com>
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-- Company : SzuWar INC
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-- Company : SzuWar INC
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-- Created : 09:45:13 16-03-2010
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-- Created : 09:45:13 16-03-2010
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-- Last update: 11:28:50 18-03-2010
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-- Last update: 23:36:11 20-03-2010
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-- Platform : Xilinx ISE 10.1.03
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-- Platform : Xilinx ISE 10.1.03
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-- Standard : VHDL'93
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-- Standard : VHDL'93
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Description:
|
-- Description:
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
| Line 24... |
Line 24... |
use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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|
|
|
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entity tb_fifo_srl_uni_1 is
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entity tb_fifo_srl_uni_1 is
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|
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end entity tb_fifo_srl_uni_1;
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end entity tb_fifo_srl_uni_1;
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|
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architecture testbench of tb_fifo_srl_uni_1 is
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architecture testbench of tb_fifo_srl_uni_1 is
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
| Line 62... |
Line 61... |
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- constants --
|
-- constants --
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
constant iDataWidth : integer := 16;
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constant iDataWidth : integer := 16;
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constant ififoWidth : integer := 4;
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constant ififoWidth : integer := 8;
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constant iInputReg : integer := 0;
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constant iInputReg : integer := 0;
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constant iOutputReg : integer := 1;
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constant iOutputReg : integer := 1;
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constant iFullFlagOfSet : integer := 1;
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constant iFullFlagOfSet : integer := 0;
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constant iEmptyFlagOfSet : integer := 1;
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constant iEmptyFlagOfSet : integer := 0;
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constant iSizeDelayCounter : integer := 6;
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constant iSizeDelayCounter : integer := 5;
|
|
|
constant iWriteDataCounter : integer := 12;
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constant iWriteDataCounter : integer := 10;
|
constant iReadDataCounter : integer := 6;
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constant iReadDataCounter : integer := 13;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- signals --
|
-- signals --
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- IN --
|
-- IN --
|
| Line 90... |
Line 89... |
signal EMPTY_FLAG_O : std_logic;
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signal EMPTY_FLAG_O : std_logic;
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signal FIFO_COUNT_O : std_logic_vector(iSizeDelayCounter - 1 downto 0);
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signal FIFO_COUNT_O : std_logic_vector(iSizeDelayCounter - 1 downto 0);
|
|
|
-- others --
|
-- others --
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signal v_count : std_logic_vector(15 downto 0) := x"0000";
|
signal v_count : std_logic_vector(15 downto 0) := x"0000";
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signal i_count_write : integer range 0 to ififoWidth := 0;
|
signal i_count_write : integer := 0;
|
|
signal i_count_read : integer := 0;
|
|
|
begin -- architecture testbench
|
begin -- architecture testbench
|
|
|
|
|
UUT: fifo_srl_uni
|
UUT: fifo_srl_uni
|
| Line 142... |
Line 142... |
|
|
if rising_edge(CLK_I) then
|
if rising_edge(CLK_I) then
|
|
|
case v_count is
|
case v_count is
|
|
|
|
when x"0001" =>
|
|
|
|
if (iWriteDataCounter + 1) > i_count_write then
|
|
|
|
DATA_I <= DATA_I + 1;
|
|
WRITE_ENABLE_I <= '1';
|
|
READ_ENABLE_I <= '0';
|
|
i_count_write <= i_count_write + 1;
|
|
|
|
else
|
|
|
|
v_count <= v_count + 1;
|
|
|
|
end if;
|
|
|
|
when x"0002" =>
|
|
|
|
DATA_I <= x"0000";
|
|
WRITE_ENABLE_I <= '0';
|
|
READ_ENABLE_I <= '0';
|
|
v_count <= v_count + 1;
|
|
|
when x"0003" =>
|
when x"0003" =>
|
|
|
DATA_I <= x"0010";
|
DATA_I <= x"0010";
|
WRITE_ENABLE_I <= '1';
|
WRITE_ENABLE_I <= '1';
|
READ_ENABLE_I <= '0';
|
READ_ENABLE_I <= '0';
|
| Line 174... |
Line 196... |
|
|
when x"0007" =>
|
when x"0007" =>
|
|
|
DATA_I <= x"0000";
|
DATA_I <= x"0000";
|
WRITE_ENABLE_I <= '0';
|
WRITE_ENABLE_I <= '0';
|
READ_ENABLE_I <= '1';
|
READ_ENABLE_I <= '0';
|
v_count <= v_count + 1;
|
v_count <= v_count + 1;
|
|
|
when x"0008" =>
|
when x"0008" =>
|
|
|
DATA_I <= x"0000";
|
DATA_I <= x"0000";
|
WRITE_ENABLE_I <= '0';
|
WRITE_ENABLE_I <= '0';
|
READ_ENABLE_I <= '0';
|
READ_ENABLE_I <= '0';
|
v_count <= v_count + 1;
|
v_count <= v_count + 1;
|
|
|
|
when x"0010" =>
|
|
|
|
if (iReadDataCounter + 1) > i_count_read then
|
|
|
|
DATA_I <= DATA_I;
|
|
WRITE_ENABLE_I <= '0';
|
|
READ_ENABLE_I <= '1';
|
|
i_count_read <= i_count_read + 1;
|
|
|
|
else
|
|
|
|
v_count <= v_count + 1;
|
|
|
|
end if;
|
|
|
|
when x"0011" =>
|
|
|
|
DATA_I <= x"0000";
|
|
WRITE_ENABLE_I <= '0';
|
|
READ_ENABLE_I <= '0';
|
|
v_count <= v_count + 1;
|
|
|
when others =>
|
when others =>
|
|
|
WRITE_ENABLE_I <= WRITE_ENABLE_I;
|
WRITE_ENABLE_I <= WRITE_ENABLE_I;
|
READ_ENABLE_I <= READ_ENABLE_I;
|
READ_ENABLE_I <= READ_ENABLE_I;
|
