-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Title : Testbench for fifo_srl_uni.vhd
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-- Title : Testbench for fifo_srl_uni.vhd
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-- Project :
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-- Project :
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File : tb_fifo_srl_uni_1.vhd
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-- File : tb_fifo_srl_uni_1.vhd
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-- Author : Tomasz Turek <tomasz.turek@gmail.com>
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-- Author : Tomasz Turek <tomasz.turek@gmail.com>
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-- Company : SzuWar INC
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-- Company : SzuWar INC
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-- Created : 09:45:13 16-03-2010
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-- Created : 09:45:13 16-03-2010
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-- Last update: 11:28:50 18-03-2010
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-- Last update: 23:36:11 20-03-2010
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-- Platform : Xilinx ISE 10.1.03
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-- Platform : Xilinx ISE 10.1.03
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-- Standard : VHDL'93
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-- Standard : VHDL'93
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Description:
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-- Description:
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Copyright (c) 2010 SzuWar INC
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-- Copyright (c) 2010 SzuWar INC
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Revisions :
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-- Date Version Author Description
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-- Date Version Author Description
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-- 09:45:13 16-03-2010 1.0 szuwarek Created
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-- 09:45:13 16-03-2010 1.0 szuwarek Created
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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entity tb_fifo_srl_uni_1 is
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entity tb_fifo_srl_uni_1 is
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end entity tb_fifo_srl_uni_1;
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end entity tb_fifo_srl_uni_1;
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architecture testbench of tb_fifo_srl_uni_1 is
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architecture testbench of tb_fifo_srl_uni_1 is
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Unit Under Test --
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-- Unit Under Test --
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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component fifo_srl_uni is
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component fifo_srl_uni is
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generic (
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generic (
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iDataWidth : integer range 1 to 32 := 17;
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iDataWidth : integer range 1 to 32 := 17;
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ififoWidth : integer range 1 to 1023 := 33;
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ififoWidth : integer range 1 to 1023 := 33;
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iInputReg : integer range 0 to 2 := 0;
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iInputReg : integer range 0 to 2 := 0;
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iOutputReg : integer range 0 to 3 := 2;
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iOutputReg : integer range 0 to 3 := 2;
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iFullFlagOfSet : integer range 0 to 1021 := 2;
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iFullFlagOfSet : integer range 0 to 1021 := 2;
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iEmptyFlagOfSet : integer range 0 to 1021 := 5;
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iEmptyFlagOfSet : integer range 0 to 1021 := 5;
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iSizeDelayCounter : integer range 5 to 11 := 6
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iSizeDelayCounter : integer range 5 to 11 := 6
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);
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);
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port (
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port (
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CLK_I : in std_logic;
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CLK_I : in std_logic;
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DATA_I : in std_logic_vector(iDataWidth - 1 downto 0);
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DATA_I : in std_logic_vector(iDataWidth - 1 downto 0);
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DATA_O : out std_logic_vector(iDataWidth - 1 downto 0);
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DATA_O : out std_logic_vector(iDataWidth - 1 downto 0);
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WRITE_ENABLE_I : in std_logic;
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WRITE_ENABLE_I : in std_logic;
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READ_ENABLE_I : in std_logic;
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READ_ENABLE_I : in std_logic;
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READ_VALID_O : out std_logic;
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READ_VALID_O : out std_logic;
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FIFO_COUNT_O : out std_logic_vector(iSizeDelayCounter - 1 downto 0);
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FIFO_COUNT_O : out std_logic_vector(iSizeDelayCounter - 1 downto 0);
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FULL_FLAG_O : out std_logic;
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FULL_FLAG_O : out std_logic;
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EMPTY_FLAG_O : out std_logic
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EMPTY_FLAG_O : out std_logic
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);
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);
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end component fifo_srl_uni;
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end component fifo_srl_uni;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- constants --
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-- constants --
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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constant iDataWidth : integer := 16;
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constant iDataWidth : integer := 16;
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constant ififoWidth : integer := 4;
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constant ififoWidth : integer := 8;
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constant iInputReg : integer := 0;
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constant iInputReg : integer := 0;
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constant iOutputReg : integer := 1;
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constant iOutputReg : integer := 1;
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constant iFullFlagOfSet : integer := 1;
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constant iFullFlagOfSet : integer := 0;
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constant iEmptyFlagOfSet : integer := 1;
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constant iEmptyFlagOfSet : integer := 0;
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constant iSizeDelayCounter : integer := 6;
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constant iSizeDelayCounter : integer := 5;
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constant iWriteDataCounter : integer := 12;
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constant iWriteDataCounter : integer := 10;
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constant iReadDataCounter : integer := 6;
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constant iReadDataCounter : integer := 13;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- signals --
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-- signals --
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- IN --
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-- IN --
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signal CLK_I : std_logic := '0';
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signal CLK_I : std_logic := '0';
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signal WRITE_ENABLE_I : std_logic := '0';
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signal WRITE_ENABLE_I : std_logic := '0';
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signal READ_ENABLE_I : std_logic := '0';
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signal READ_ENABLE_I : std_logic := '0';
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signal DATA_I : std_logic_vector(iDataWidth - 1 downto 0) := (others => '0');
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signal DATA_I : std_logic_vector(iDataWidth - 1 downto 0) := (others => '0');
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-- OUT --
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-- OUT --
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signal DATA_O : std_logic_vector(iDataWidth - 1 downto 0);
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signal DATA_O : std_logic_vector(iDataWidth - 1 downto 0);
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signal READ_VALID_O : std_logic;
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signal READ_VALID_O : std_logic;
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signal FULL_FLAG_O : std_logic;
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signal FULL_FLAG_O : std_logic;
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signal EMPTY_FLAG_O : std_logic;
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signal EMPTY_FLAG_O : std_logic;
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signal FIFO_COUNT_O : std_logic_vector(iSizeDelayCounter - 1 downto 0);
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signal FIFO_COUNT_O : std_logic_vector(iSizeDelayCounter - 1 downto 0);
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-- others --
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-- others --
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signal v_count : std_logic_vector(15 downto 0) := x"0000";
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signal v_count : std_logic_vector(15 downto 0) := x"0000";
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signal i_count_write : integer range 0 to ififoWidth := 0;
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signal i_count_write : integer := 0;
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signal i_count_read : integer := 0;
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begin -- architecture testbench
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begin -- architecture testbench
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UUT: fifo_srl_uni
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UUT: fifo_srl_uni
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generic map (
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generic map (
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iDataWidth => iDataWidth,
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iDataWidth => iDataWidth,
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ififoWidth => ififoWidth,
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ififoWidth => ififoWidth,
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iInputReg => iInputReg,
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iInputReg => iInputReg,
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iOutputReg => iOutputReg,
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iOutputReg => iOutputReg,
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iFullFlagOfSet => iFullFlagOfSet,
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iFullFlagOfSet => iFullFlagOfSet,
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iEmptyFlagOfSet => iEmptyFlagOfSet,
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iEmptyFlagOfSet => iEmptyFlagOfSet,
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iSizeDelayCounter => iSizeDelayCounter
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iSizeDelayCounter => iSizeDelayCounter
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)
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)
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port map(
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port map(
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CLK_I => CLK_I,
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CLK_I => CLK_I,
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DATA_I => DATA_I,
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DATA_I => DATA_I,
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DATA_O => DATA_O,
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DATA_O => DATA_O,
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WRITE_ENABLE_I => WRITE_ENABLE_I,
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WRITE_ENABLE_I => WRITE_ENABLE_I,
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READ_ENABLE_I => READ_ENABLE_I,
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READ_ENABLE_I => READ_ENABLE_I,
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READ_VALID_O => READ_VALID_O,
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READ_VALID_O => READ_VALID_O,
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FIFO_COUNT_O => FIFO_COUNT_O,
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FIFO_COUNT_O => FIFO_COUNT_O,
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FULL_FLAG_O => FULL_FLAG_O,
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FULL_FLAG_O => FULL_FLAG_O,
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EMPTY_FLAG_O => EMPTY_FLAG_O
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EMPTY_FLAG_O => EMPTY_FLAG_O
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);
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);
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StimulationProcess : process
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StimulationProcess : process
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begin
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begin
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for i in 0 to 1000000 loop
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for i in 0 to 1000000 loop
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CLK_I <= not CLK_I;
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CLK_I <= not CLK_I;
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wait for 5 ns;
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wait for 5 ns;
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end loop;
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end loop;
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wait;
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wait;
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end process StimulationProcess;
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end process StimulationProcess;
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T0: process (CLK_I) is
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T0: process (CLK_I) is
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begin -- process T0
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begin -- process T0
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if rising_edge(CLK_I) then
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if rising_edge(CLK_I) then
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case v_count is
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case v_count is
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when x"0001" =>
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if (iWriteDataCounter + 1) > i_count_write then
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DATA_I <= DATA_I + 1;
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WRITE_ENABLE_I <= '1';
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READ_ENABLE_I <= '0';
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i_count_write <= i_count_write + 1;
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else
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v_count <= v_count + 1;
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end if;
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when x"0002" =>
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DATA_I <= x"0000";
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WRITE_ENABLE_I <= '0';
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READ_ENABLE_I <= '0';
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v_count <= v_count + 1;
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when x"0003" =>
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when x"0003" =>
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DATA_I <= x"0010";
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DATA_I <= x"0010";
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WRITE_ENABLE_I <= '1';
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WRITE_ENABLE_I <= '1';
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READ_ENABLE_I <= '0';
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READ_ENABLE_I <= '0';
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v_count <= v_count + 1;
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v_count <= v_count + 1;
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when x"0004" =>
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when x"0004" =>
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DATA_I <= x"0200";
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DATA_I <= x"0200";
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WRITE_ENABLE_I <= '1';
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WRITE_ENABLE_I <= '1';
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READ_ENABLE_I <= '0';
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READ_ENABLE_I <= '0';
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v_count <= v_count + 1;
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v_count <= v_count + 1;
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when x"0005" =>
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when x"0005" =>
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DATA_I <= x"0100";
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DATA_I <= x"0100";
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WRITE_ENABLE_I <= '1';
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WRITE_ENABLE_I <= '1';
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READ_ENABLE_I <= '0';
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READ_ENABLE_I <= '0';
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v_count <= v_count + 1;
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v_count <= v_count + 1;
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when x"0006" =>
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when x"0006" =>
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DATA_I <= x"0000";
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DATA_I <= x"0000";
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WRITE_ENABLE_I <= '0';
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WRITE_ENABLE_I <= '0';
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READ_ENABLE_I <= '0';
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READ_ENABLE_I <= '0';
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v_count <= v_count + 1;
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v_count <= v_count + 1;
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when x"0007" =>
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when x"0007" =>
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DATA_I <= x"0000";
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DATA_I <= x"0000";
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WRITE_ENABLE_I <= '0';
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WRITE_ENABLE_I <= '0';
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READ_ENABLE_I <= '1';
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READ_ENABLE_I <= '0';
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v_count <= v_count + 1;
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v_count <= v_count + 1;
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when x"0008" =>
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when x"0008" =>
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DATA_I <= x"0000";
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WRITE_ENABLE_I <= '0';
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READ_ENABLE_I <= '0';
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v_count <= v_count + 1;
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when x"0010" =>
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if (iReadDataCounter + 1) > i_count_read then
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DATA_I <= DATA_I;
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WRITE_ENABLE_I <= '0';
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READ_ENABLE_I <= '1';
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i_count_read <= i_count_read + 1;
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else
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v_count <= v_count + 1;
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end if;
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when x"0011" =>
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DATA_I <= x"0000";
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DATA_I <= x"0000";
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WRITE_ENABLE_I <= '0';
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WRITE_ENABLE_I <= '0';
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READ_ENABLE_I <= '0';
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READ_ENABLE_I <= '0';
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v_count <= v_count + 1;
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v_count <= v_count + 1;
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when others =>
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when others =>
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WRITE_ENABLE_I <= WRITE_ENABLE_I;
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WRITE_ENABLE_I <= WRITE_ENABLE_I;
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READ_ENABLE_I <= READ_ENABLE_I;
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READ_ENABLE_I <= READ_ENABLE_I;
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v_count <= v_count + 1;
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v_count <= v_count + 1;
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end case;
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end case;
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end if;
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end if;
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end process T0;
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end process T0;
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end architecture testbench;
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end architecture testbench;
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