--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--This file is part of fpga_gpib_controller.
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--
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-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- Fpga_gpib_controller is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
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--------------------------------------------------------------------------------
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-- Entity: Uart
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-- Entity: Uart
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-- Date:2011-11-26
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-- Date:2011-11-26
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-- Author: apaluch
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-- Author: Andrzej Paluch
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--
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--
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-- Description ${cursor}
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-- Description ${cursor}
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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entity Uart is
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entity Uart is
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port (
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port (
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reset : in std_logic;
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reset : in std_logic;
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clk : in std_logic;
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clk : in std_logic;
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---------- UART ---------------
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---------- UART ---------------
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RX : in std_logic;
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RX : in std_logic;
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TX : out std_logic;
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TX : out std_logic;
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---------- gpib ---------------
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---------- gpib ---------------
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data_out : out std_logic_vector(7 downto 0);
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data_out : out std_logic_vector(7 downto 0);
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data_out_ready : out std_logic;
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data_out_ready : out std_logic;
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data_in : in std_logic_vector(7 downto 0);
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data_in : in std_logic_vector(7 downto 0);
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data_in_ready : in std_logic;
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data_in_ready : in std_logic;
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ready_to_send : out std_logic
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ready_to_send : out std_logic
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);
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);
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end Uart;
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end Uart;
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architecture arch of Uart is
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architecture arch of Uart is
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constant BIT_TIME : integer :=
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constant BIT_TIME : integer :=
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-- 115200
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-- 115200
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--572
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--572
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-- 921600
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-- 921600
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72
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72
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;
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;
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constant HALF_BIT_TIME : integer := BIT_TIME / 2;
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constant HALF_BIT_TIME : integer := BIT_TIME / 2;
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type RX_STATES is (
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type RX_STATES is (
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ST_RX_IDLE,
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ST_RX_IDLE,
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ST_RX_HALF_START,
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ST_RX_HALF_START,
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ST_RX_RECEIVE_BITS,
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ST_RX_RECEIVE_BITS,
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ST_RX_RECEIVE_STOP_BIT
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ST_RX_RECEIVE_STOP_BIT
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);
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);
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type TX_STATES is (
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type TX_STATES is (
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ST_TX_IDLE,
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ST_TX_IDLE,
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ST_TX_SEND_BITS,
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ST_TX_SEND_BITS,
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ST_TX_SEND_STOP_BIT
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ST_TX_SEND_STOP_BIT
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);
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);
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signal syncRX : std_logic;
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signal syncRX : std_logic;
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signal rxState : RX_STATES;
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signal rxState : RX_STATES;
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signal lastRx : std_logic;
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signal lastRx : std_logic;
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signal rxTimeCounter : integer range 0 to BIT_TIME;
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signal rxTimeCounter : integer range 0 to BIT_TIME;
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signal rxBitCounter : integer range 0 to 7;
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signal rxBitCounter : integer range 0 to 7;
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signal innerBuf : std_logic_vector(6 downto 0);
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signal innerBuf : std_logic_vector(6 downto 0);
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signal txState : TX_STATES;
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signal txState : TX_STATES;
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signal lastData_in_ready : std_logic;
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signal lastData_in_ready : std_logic;
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signal txTimeCounter : integer range 0 to BIT_TIME;
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signal txTimeCounter : integer range 0 to BIT_TIME;
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signal txBitCounter : integer range 0 to 8;
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signal txBitCounter : integer range 0 to 8;
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begin
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begin
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-- RX synchronizer
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-- RX synchronizer
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process(clk, RX) begin
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process(clk, RX) begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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syncRX <= RX;
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syncRX <= RX;
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end if;
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end if;
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end process;
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end process;
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-- RX
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-- RX
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process(reset, clk, syncRX) begin
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process(reset, clk, syncRX) begin
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if reset = '1' then
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if reset = '1' then
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rxState <= ST_RX_IDLE;
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rxState <= ST_RX_IDLE;
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lastRx <= syncRX;
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lastRx <= syncRX;
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data_out_ready <= '0';
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data_out_ready <= '0';
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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lastRx <= syncRX;
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lastRx <= syncRX;
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if rxTimeCounter < BIT_TIME then
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if rxTimeCounter < BIT_TIME then
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rxTimeCounter <= rxTimeCounter + 1;
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rxTimeCounter <= rxTimeCounter + 1;
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end if;
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end if;
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case rxState is
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case rxState is
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when ST_RX_IDLE =>
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when ST_RX_IDLE =>
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if lastRx /= syncRX and syncRX = '0' then
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if lastRx /= syncRX and syncRX = '0' then
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rxTimeCounter <= 1;
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rxTimeCounter <= 1;
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rxState <= ST_RX_HALF_START;
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rxState <= ST_RX_HALF_START;
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end if;
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end if;
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when ST_RX_HALF_START =>
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when ST_RX_HALF_START =>
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if rxTimeCounter >= HALF_BIT_TIME then
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if rxTimeCounter >= HALF_BIT_TIME then
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rxBitCounter <= 0;
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rxBitCounter <= 0;
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rxTimeCounter <= 1;
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rxTimeCounter <= 1;
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rxState <= ST_RX_RECEIVE_BITS;
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rxState <= ST_RX_RECEIVE_BITS;
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end if;
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end if;
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when ST_RX_RECEIVE_BITS =>
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when ST_RX_RECEIVE_BITS =>
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if rxTimeCounter >= BIT_TIME then
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if rxTimeCounter >= BIT_TIME then
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if rxBitCounter < 7 then
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if rxBitCounter < 7 then
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innerBuf(rxBitCounter) <= syncRX;
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innerBuf(rxBitCounter) <= syncRX;
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rxBitCounter <= rxBitCounter + 1;
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rxBitCounter <= rxBitCounter + 1;
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rxTimeCounter <= 1;
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rxTimeCounter <= 1;
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elsif rxBitCounter = 7 then
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elsif rxBitCounter = 7 then
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data_out(7) <= syncRX;
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data_out(7) <= syncRX;
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data_out(6 downto 0) <= innerBuf;
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data_out(6 downto 0) <= innerBuf;
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data_out_ready <= '0';
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data_out_ready <= '0';
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rxTimeCounter <= 1;
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rxTimeCounter <= 1;
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rxState <= ST_RX_RECEIVE_STOP_BIT;
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rxState <= ST_RX_RECEIVE_STOP_BIT;
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end if;
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end if;
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end if;
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end if;
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when ST_RX_RECEIVE_STOP_BIT =>
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when ST_RX_RECEIVE_STOP_BIT =>
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if rxTimeCounter >= BIT_TIME then
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if rxTimeCounter >= BIT_TIME then
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data_out_ready <= '1';
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data_out_ready <= '1';
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rxState <= ST_RX_IDLE;
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rxState <= ST_RX_IDLE;
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end if;
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end if;
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when others =>
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when others =>
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rxState <= ST_RX_IDLE;
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rxState <= ST_RX_IDLE;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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-- TX
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-- TX
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process(reset, clk, data_in_ready) begin
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process(reset, clk, data_in_ready) begin
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if reset = '1' then
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if reset = '1' then
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TX <= '1';
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TX <= '1';
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ready_to_send <= '1';
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ready_to_send <= '1';
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txState <= ST_TX_IDLE;
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txState <= ST_TX_IDLE;
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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lastData_in_ready <= data_in_ready;
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lastData_in_ready <= data_in_ready;
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if txTimeCounter < BIT_TIME then
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if txTimeCounter < BIT_TIME then
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txTimeCounter <= txTimeCounter + 1;
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txTimeCounter <= txTimeCounter + 1;
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end if;
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end if;
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case txState is
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case txState is
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when ST_TX_IDLE =>
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when ST_TX_IDLE =>
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if lastData_in_ready /= data_in_ready and
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if lastData_in_ready /= data_in_ready and
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data_in_ready = '1' then
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data_in_ready = '1' then
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TX <= '0';
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TX <= '0';
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txTimeCounter <= 1;
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txTimeCounter <= 1;
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txBitCounter <= 0;
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txBitCounter <= 0;
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ready_to_send <= '0';
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ready_to_send <= '0';
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txState <= ST_TX_SEND_BITS;
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txState <= ST_TX_SEND_BITS;
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end if;
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end if;
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when ST_TX_SEND_BITS =>
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when ST_TX_SEND_BITS =>
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if txTimeCounter >= BIT_TIME then
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if txTimeCounter >= BIT_TIME then
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if txBitCounter < 8 then
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if txBitCounter < 8 then
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TX <= data_in(txBitCounter);
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TX <= data_in(txBitCounter);
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txBitCounter <= txBitCounter + 1;
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txBitCounter <= txBitCounter + 1;
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txTimeCounter <= 1;
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txTimeCounter <= 1;
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elsif txBitCounter = 8 then
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elsif txBitCounter = 8 then
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TX <= '1';
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TX <= '1';
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txTimeCounter <= 1;
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txTimeCounter <= 1;
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txState <= ST_TX_SEND_STOP_BIT;
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txState <= ST_TX_SEND_STOP_BIT;
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end if;
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end if;
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end if;
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end if;
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when ST_TX_SEND_STOP_BIT =>
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when ST_TX_SEND_STOP_BIT =>
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if txTimeCounter >= BIT_TIME then
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if txTimeCounter >= BIT_TIME then
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ready_to_send <= '1';
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ready_to_send <= '1';
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txState <= ST_TX_IDLE;
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txState <= ST_TX_IDLE;
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end if;
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end if;
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when others =>
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when others =>
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txState <= ST_TX_IDLE;
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txState <= ST_TX_IDLE;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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end arch;
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end arch;
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