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--------------------------------------------------------------------------------
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--This file is part of fpga_gpib_controller.
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--
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-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- Fpga_gpib_controller is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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-- Company:
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-- author: Andrzej Paluch
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-- Engineer:
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--
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--
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-- Create Date: 01:04:57 10/03/2011
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-- Create Date: 01:04:57 10/03/2011
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-- Design Name:
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-- Design Name:
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-- Module Name: if_func_DC - Behavioral
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-- Module Name: if_func_DC - Behavioral
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-- Project Name:
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-- Project Name:
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-- Target Devices:
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-- Target Devices:
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-- Tool versions:
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-- Tool versions:
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-- Description:
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-- Description:
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--
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--
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-- Dependencies:
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-- Dependencies:
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--
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--
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-- Revision:
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-- Revision:
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-- Revision 0.01 - File Created
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-- Revision 0.01 - File Created
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-- Additional Comments:
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-- Additional Comments:
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--
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--
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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---- Uncomment the following library declaration if instantiating
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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entity if_func_DC is
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entity if_func_DC is
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port(
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port(
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-- device inputs
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-- device inputs
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clk : in std_logic; -- clock
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clk : in std_logic; -- clock
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-- state inputs
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-- state inputs
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LADS : in std_logic; -- listener addressed state (L or LE)
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LADS : in std_logic; -- listener addressed state (L or LE)
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ACDS : in std_logic; -- accept data state (AH)
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ACDS : in std_logic; -- accept data state (AH)
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-- instructions
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-- instructions
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DCL : in std_logic; -- my listen address
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DCL : in std_logic; -- my listen address
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SDC : in std_logic; -- unlisten
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SDC : in std_logic; -- unlisten
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-- local instructions
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-- local instructions
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clr : out std_logic -- clear device
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clr : out std_logic -- clear device
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);
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);
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end if_func_DC;
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end if_func_DC;
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architecture Behavioral of if_func_DC is
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architecture Behavioral of if_func_DC is
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-- states
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-- states
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type DC_STATE is (
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type DC_STATE is (
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-- device clear idle state
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-- device clear idle state
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ST_DCIS,
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ST_DCIS,
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-- device clear active state
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-- device clear active state
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ST_DCAS
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ST_DCAS
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);
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);
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-- current state
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-- current state
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signal current_state : DC_STATE;
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signal current_state : DC_STATE;
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-- predicates
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-- predicates
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signal pred1 : boolean;
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signal pred1 : boolean;
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signal pred2 : boolean;
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signal pred2 : boolean;
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begin
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begin
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-- state machine process
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-- state machine process
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process(clk) begin
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process(clk) begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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case current_state is
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case current_state is
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------------------
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------------------
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when ST_DCIS =>
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when ST_DCIS =>
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if pred1 then
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if pred1 then
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current_state <= ST_DCAS;
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current_state <= ST_DCAS;
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end if;
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end if;
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------------------
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------------------
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when ST_DCAS =>
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when ST_DCAS =>
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if pred2 then
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if pred2 then
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current_state <= ST_DCIS;
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current_state <= ST_DCIS;
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end if;
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end if;
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------------------
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------------------
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when others =>
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when others =>
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current_state <= ST_DCIS;
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current_state <= ST_DCIS;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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-- predicates
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-- predicates
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pred1 <= (DCL='1' or (SDC='1' and LADS='1')) and ACDS='1';
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pred1 <= (DCL='1' or (SDC='1' and LADS='1')) and ACDS='1';
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pred2 <= not pred1;
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pred2 <= not pred1;
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-- clr generator
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-- clr generator
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with current_state select
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with current_state select
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clr <=
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clr <=
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'1' when ST_DCAS,
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'1' when ST_DCAS,
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'0' when others;
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'0' when others;
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end Behavioral;
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end Behavioral;
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