--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--This file is part of fpga_gpib_controller.
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--
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-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- Fpga_gpib_controller is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
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--------------------------------------------------------------------------------
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-- Entity: if_func_L_LE
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-- Entity: if_func_L_LE
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-- Date: 01:04:57 10/01/2011
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-- Date: 01:04:57 10/01/2011
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-- Author: apaluch
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-- Author: Andrzej Paluch
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.utilPkg.all;
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use work.utilPkg.all;
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entity if_func_L_LE is
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entity if_func_L_LE is
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port(
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port(
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-- clock
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-- clock
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clk : in std_logic; -- clock
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clk : in std_logic; -- clock
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-- function settings
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-- function settings
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isLE : in std_logic;
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isLE : in std_logic;
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-- local commands
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-- local commands
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pon : in std_logic; -- power on
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pon : in std_logic; -- power on
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ltn : in std_logic; -- listen
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ltn : in std_logic; -- listen
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lun : in std_logic; -- local unlisten
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lun : in std_logic; -- local unlisten
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lon : in std_logic; -- listen only
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lon : in std_logic; -- listen only
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-- state inputs
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-- state inputs
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ACDS : in std_logic; -- accept data state (AH)
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ACDS : in std_logic; -- accept data state (AH)
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CACS : in std_logic; -- controller active state (C)
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CACS : in std_logic; -- controller active state (C)
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TPAS : in std_logic; -- talker primary address state (T)
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TPAS : in std_logic; -- talker primary address state (T)
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-- remote commands
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-- remote commands
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ATN : in std_logic; -- attention
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ATN : in std_logic; -- attention
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IFC : in std_logic; -- interface clear
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IFC : in std_logic; -- interface clear
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MLA : in std_logic; -- my listen address
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MLA : in std_logic; -- my listen address
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MTA : in std_logic; -- my talk address
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MTA : in std_logic; -- my talk address
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UNL : in std_logic; -- unlisten
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UNL : in std_logic; -- unlisten
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PCG : in std_logic; -- primary command group
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PCG : in std_logic; -- primary command group
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MSA : in std_logic; -- my secondary address
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MSA : in std_logic; -- my secondary address
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-- reported states
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-- reported states
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LACS : out std_logic; -- listener active state
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LACS : out std_logic; -- listener active state
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LADS : out std_logic; -- listener addressed state
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LADS : out std_logic; -- listener addressed state
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LPAS : out std_logic -- listener primary addressed state
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LPAS : out std_logic -- listener primary addressed state
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;debug1 : out std_logic
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;debug1 : out std_logic
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);
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);
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end if_func_L_LE;
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end if_func_L_LE;
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architecture Behavioral of if_func_L_LE is
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architecture Behavioral of if_func_L_LE is
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-- states
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-- states
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type LE_STATE_1 is (
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type LE_STATE_1 is (
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-- listener idle state
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-- listener idle state
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ST_LIDS,
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ST_LIDS,
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-- listener addressed state
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-- listener addressed state
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ST_LADS,
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ST_LADS,
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-- listener active state
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-- listener active state
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ST_LACS
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ST_LACS
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);
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);
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-- states
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-- states
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type LE_STATE_2 is (
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type LE_STATE_2 is (
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-- listener primary idle state
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-- listener primary idle state
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ST_LPIS,
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ST_LPIS,
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-- listener primary addressed state
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-- listener primary addressed state
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ST_LPAS
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ST_LPAS
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);
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);
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-- current state
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-- current state
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signal current_state_1 : LE_STATE_1;
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signal current_state_1 : LE_STATE_1;
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signal current_state_2 : LE_STATE_2;
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signal current_state_2 : LE_STATE_2;
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-- predicates
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-- predicates
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signal event0, event1, event2, event3, event4 : boolean;
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signal event0, event1, event2, event3, event4 : boolean;
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begin
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begin
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debug1 <= to_stdl(current_state_1 = ST_LACS) or
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debug1 <= to_stdl(current_state_1 = ST_LACS) or
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to_stdl(current_state_1 = ST_LADS);
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to_stdl(current_state_1 = ST_LADS);
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-- state machine process - L_STATE_1
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-- state machine process - L_STATE_1
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process(pon, clk) begin
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process(pon, clk) begin
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if pon = '1' then
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if pon = '1' then
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current_state_1 <= ST_LIDS;
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current_state_1 <= ST_LIDS;
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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case current_state_1 is
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case current_state_1 is
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------------------
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------------------
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when ST_LIDS =>
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when ST_LIDS =>
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if event0 then
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if event0 then
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-- no state change
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-- no state change
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elsif event1 then
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elsif event1 then
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current_state_1 <= ST_LADS;
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current_state_1 <= ST_LADS;
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end if;
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end if;
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------------------
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------------------
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when ST_LADS =>
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when ST_LADS =>
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if event0 then
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if event0 then
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current_state_1 <= ST_LIDS;
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current_state_1 <= ST_LIDS;
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elsif event2 then
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elsif event2 then
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current_state_1 <= ST_LIDS;
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current_state_1 <= ST_LIDS;
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elsif ATN='0' then
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elsif ATN='0' then
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current_state_1 <= ST_LACS;
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current_state_1 <= ST_LACS;
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end if;
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end if;
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------------------
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------------------
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when ST_LACS =>
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when ST_LACS =>
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if event0 then
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if event0 then
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current_state_1 <= ST_LIDS;
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current_state_1 <= ST_LIDS;
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elsif ATN='1' then
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elsif ATN='1' then
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current_state_1 <= ST_LADS;
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current_state_1 <= ST_LADS;
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end if;
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end if;
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------------------
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------------------
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when others =>
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when others =>
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current_state_1 <= ST_LIDS;
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current_state_1 <= ST_LIDS;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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-- state machine process - L_STATE_2
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-- state machine process - L_STATE_2
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process(pon, clk) begin
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process(pon, clk) begin
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if pon = '1' then
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if pon = '1' then
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current_state_2 <= ST_LPIS;
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current_state_2 <= ST_LPIS;
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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case current_state_2 is
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case current_state_2 is
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------------------
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------------------
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when ST_LPIS =>
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when ST_LPIS =>
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if event0 then
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if event0 then
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-- no state change
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-- no state change
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elsif event3 then
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elsif event3 then
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current_state_2 <= ST_LPAS;
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current_state_2 <= ST_LPAS;
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end if;
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end if;
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------------------
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------------------
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when ST_LPAS =>
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when ST_LPAS =>
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if event0 then
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if event0 then
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current_state_2 <= ST_LPIS;
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current_state_2 <= ST_LPIS;
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elsif event4 then
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elsif event4 then
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current_state_2 <= ST_LPIS;
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current_state_2 <= ST_LPIS;
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end if;
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end if;
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------------------
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------------------
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when others =>
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when others =>
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current_state_2 <= ST_LPIS;
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current_state_2 <= ST_LPIS;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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-- events
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-- events
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event0 <= IFC='1';
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event0 <= IFC='1';
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event1 <= (isLE='1' and (
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event1 <= (isLE='1' and (
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lon='1' or (ltn='1' and CACS='1') or
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lon='1' or (ltn='1' and CACS='1') or
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(MSA='1' and current_state_2=ST_LPAS and ACDS='1')
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(MSA='1' and current_state_2=ST_LPAS and ACDS='1')
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)) or
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)) or
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(isLE='0' and (
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(isLE='0' and (
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lon='1' or (MLA='1' and ACDS='1') or (ltn='1' and CACS='1')
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lon='1' or (MLA='1' and ACDS='1') or (ltn='1' and CACS='1')
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));
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));
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event2 <= (isLE='1' and (
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event2 <= (isLE='1' and (
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(UNL='1' and ACDS='1') or
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(UNL='1' and ACDS='1') or
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(lun='1' and CACS='1') or
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(lun='1' and CACS='1') or
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(MSA='1' and TPAS='1' and ACDS='1')
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(MSA='1' and TPAS='1' and ACDS='1')
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)) or
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)) or
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(isLE='0' and (
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(isLE='0' and (
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(UNL='1' and ACDS='1') or
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(UNL='1' and ACDS='1') or
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(MTA='1' and ACDS='1') or
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(MTA='1' and ACDS='1') or
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(lun='1' and CACS='1')
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(lun='1' and CACS='1')
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));
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));
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event3 <= MLA='1' and ACDS='1';
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event3 <= MLA='1' and ACDS='1';
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event4 <= PCG='1' and MLA='0' and ACDS='1';
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event4 <= PCG='1' and MLA='0' and ACDS='1';
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LACS <= to_stdl(current_state_1 = ST_LACS);
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LACS <= to_stdl(current_state_1 = ST_LACS);
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LADS <= to_stdl(current_state_1 = ST_LADS);
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LADS <= to_stdl(current_state_1 = ST_LADS);
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LPAS <= to_stdl(current_state_2 = ST_LPAS);
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LPAS <= to_stdl(current_state_2 = ST_LPAS);
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end Behavioral;
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end Behavioral;
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