|
--------------------------------------------------------------------------------
|
|
--This file is part of fpga_gpib_controller.
|
|
--
|
|
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
|
|
-- it under the terms of the GNU General Public License as published by
|
|
-- the Free Software Foundation, either version 3 of the License, or
|
|
-- (at your option) any later version.
|
|
--
|
|
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
|
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
-- GNU General Public License for more details.
|
|
|
|
-- You should have received a copy of the GNU General Public License
|
|
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
|
----------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------
|
-- Company:
|
-- Author: Andrzej Paluch
|
-- Engineer:
|
|
--
|
--
|
-- Create Date: 01:04:57 10/01/2011
|
-- Create Date: 01:04:57 10/01/2011
|
-- Design Name:
|
-- Design Name:
|
-- Module Name: if_func_SR - Behavioral
|
-- Module Name: if_func_SR - Behavioral
|
-- Project Name:
|
-- Project Name:
|
-- Target Devices:
|
-- Target Devices:
|
-- Tool versions:
|
-- Tool versions:
|
-- Description:
|
-- Description:
|
--
|
--
|
-- Dependencies:
|
-- Dependencies:
|
--
|
--
|
-- Revision:
|
-- Revision:
|
-- Revision 0.01 - File Created
|
-- Revision 0.01 - File Created
|
-- Additional Comments:
|
-- Additional Comments:
|
--
|
--
|
----------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------
|
library IEEE;
|
library IEEE;
|
use IEEE.STD_LOGIC_1164.ALL;
|
use IEEE.STD_LOGIC_1164.ALL;
|
|
|
---- Uncomment the following library declaration if instantiating
|
---- Uncomment the following library declaration if instantiating
|
---- any Xilinx primitives in this code.
|
---- any Xilinx primitives in this code.
|
--library UNISIM;
|
--library UNISIM;
|
--use UNISIM.VComponents.all;
|
--use UNISIM.VComponents.all;
|
|
|
entity if_func_SR is
|
entity if_func_SR is
|
port(
|
port(
|
-- device inputs
|
-- device inputs
|
clk : in std_logic; -- clock
|
clk : in std_logic; -- clock
|
pon : in std_logic; -- power on
|
pon : in std_logic; -- power on
|
rsv : in std_logic; -- service request
|
rsv : in std_logic; -- service request
|
-- state inputs
|
-- state inputs
|
SPAS : in std_logic; -- serial poll active state (T or TE)
|
SPAS : in std_logic; -- serial poll active state (T or TE)
|
-- output instructions
|
-- output instructions
|
SRQ : out std_logic; -- service request
|
SRQ : out std_logic; -- service request
|
-- reported states
|
-- reported states
|
APRS : out std_logic -- affirmative poll response state
|
APRS : out std_logic -- affirmative poll response state
|
);
|
);
|
end if_func_SR;
|
end if_func_SR;
|
|
|
architecture Behavioral of if_func_SR is
|
architecture Behavioral of if_func_SR is
|
|
|
-- states
|
-- states
|
type SR_STATE is (
|
type SR_STATE is (
|
-- negative poll response state
|
-- negative poll response state
|
ST_NPRS,
|
ST_NPRS,
|
-- service request state
|
-- service request state
|
ST_SRQS,
|
ST_SRQS,
|
-- affirmative poll response state
|
-- affirmative poll response state
|
ST_APRS
|
ST_APRS
|
);
|
);
|
|
|
-- current state
|
-- current state
|
signal current_state : SR_STATE;
|
signal current_state : SR_STATE;
|
|
|
-- predicates
|
-- predicates
|
signal pred1 : boolean;
|
signal pred1 : boolean;
|
signal pred2 : boolean;
|
signal pred2 : boolean;
|
|
|
begin
|
begin
|
|
|
-- state machine process
|
-- state machine process
|
process(pon, clk) begin
|
process(pon, clk) begin
|
|
|
if pon = '1' then
|
if pon = '1' then
|
|
|
current_state <= ST_NPRS;
|
current_state <= ST_NPRS;
|
|
|
elsif rising_edge(clk) then
|
elsif rising_edge(clk) then
|
|
|
case current_state is
|
case current_state is
|
------------------
|
------------------
|
when ST_NPRS =>
|
when ST_NPRS =>
|
if pred1 then
|
if pred1 then
|
current_state <= ST_SRQS;
|
current_state <= ST_SRQS;
|
end if;
|
end if;
|
------------------
|
------------------
|
when ST_SRQS =>
|
when ST_SRQS =>
|
if pred2 then
|
if pred2 then
|
current_state <= ST_NPRS;
|
current_state <= ST_NPRS;
|
elsif SPAS='1' then
|
elsif SPAS='1' then
|
current_state <= ST_APRS;
|
current_state <= ST_APRS;
|
end if;
|
end if;
|
------------------
|
------------------
|
when ST_APRS =>
|
when ST_APRS =>
|
if pred2 then
|
if pred2 then
|
current_state <= ST_NPRS;
|
current_state <= ST_NPRS;
|
end if;
|
end if;
|
------------------
|
------------------
|
when others =>
|
when others =>
|
current_state <= ST_NPRS;
|
current_state <= ST_NPRS;
|
end case;
|
end case;
|
end if;
|
end if;
|
|
|
end process;
|
end process;
|
|
|
-- predicates
|
-- predicates
|
pred1 <= rsv='1' and SPAS='0';
|
pred1 <= rsv='1' and SPAS='0';
|
pred2 <= rsv='0' and SPAS='0';
|
pred2 <= rsv='0' and SPAS='0';
|
|
|
-- APRS generator
|
-- APRS generator
|
with current_state select
|
with current_state select
|
APRS <=
|
APRS <=
|
'1' when ST_APRS,
|
'1' when ST_APRS,
|
'0' when others;
|
'0' when others;
|
|
|
-- SRQ generator
|
-- SRQ generator
|
with current_state select
|
with current_state select
|
SRQ <=
|
SRQ <=
|
'1' when ST_SRQS,
|
'1' when ST_SRQS,
|
'0' when others;
|
'0' when others;
|
|
|
end Behavioral;
|
end Behavioral;
|
|
|
