--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--This file is part of fpga_gpib_controller.
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--
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-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- Fpga_gpib_controller is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
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--------------------------------------------------------------------------------
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-- Entity: EdgeDetector
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-- Entity: EdgeDetector
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-- Date:2011-11-25
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-- Date:2011-11-25
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-- Author: Administrator
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-- Author: Andrzej Paluch
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--
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--
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-- Description ${cursor}
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-- Description ${cursor}
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use work.helperComponents.all;
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use work.helperComponents.all;
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entity EdgeDetector is
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entity EdgeDetector is
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generic (
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generic (
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RISING : std_logic := '1';
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RISING : std_logic := '1';
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FALLING : std_logic := '0';
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FALLING : std_logic := '0';
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PULSE_WIDTH : integer := 10
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PULSE_WIDTH : integer := 10
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);
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);
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port (
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port (
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reset : in std_logic;
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reset : in std_logic;
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clk : in std_logic;
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clk : in std_logic;
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in_data : in std_logic;
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in_data : in std_logic;
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pulse : out std_logic
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pulse : out std_logic
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);
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);
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end EdgeDetector;
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end EdgeDetector;
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architecture arch of EdgeDetector is
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architecture arch of EdgeDetector is
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signal t_i, t_o : std_logic;
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signal t_i, t_o : std_logic;
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signal lastData : std_logic;
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signal lastData : std_logic;
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begin
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begin
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process(reset, clk, t_o, in_data) begin
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process(reset, clk, t_o, in_data) begin
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if reset = '1' then
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if reset = '1' then
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t_i <= t_o;
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t_i <= t_o;
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lastData <= in_data;
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lastData <= in_data;
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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if lastData /= in_data then
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if lastData /= in_data then
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if RISING='1' and lastData='0' and in_data='1' then
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if RISING='1' and lastData='0' and in_data='1' then
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t_i <= not t_o;
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t_i <= not t_o;
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end if;
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end if;
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if FALLING='1' and lastData='1' and in_data='0' then
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if FALLING='1' and lastData='1' and in_data='0' then
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t_i <= not t_o;
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t_i <= not t_o;
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end if;
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end if;
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end if;
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end if;
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lastData <= in_data;
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lastData <= in_data;
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end if;
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end if;
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end process;
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end process;
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spg: SinglePulseGenerator generic map (WIDTH => PULSE_WIDTH) port map (
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spg: SinglePulseGenerator generic map (WIDTH => PULSE_WIDTH) port map (
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reset => reset, clk => clk, t_in => t_i, t_out => t_o, pulse => pulse
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reset => reset, clk => clk, t_in => t_i, t_out => t_o, pulse => pulse
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);
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);
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end arch;
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end arch;
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