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--------------------------------------------------------------------------------
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--This file is part of fpga_gpib_controller.
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--
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-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- Fpga_gpib_controller is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
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--------------------------------------------------------------------------------
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-- Entity: gpibReader
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-- Entity: gpibReader
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-- Date: 2011-10-30
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-- Date: 2011-10-30
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-- Author: apaluch
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-- Author: Andrzej Paluch
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use work.utilPkg.all;
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use work.utilPkg.all;
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entity gpibReader is
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entity gpibReader is
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port (
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port (
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-- clock
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-- clock
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clk : in std_logic;
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clk : in std_logic;
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-- reset
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-- reset
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reset : std_logic;
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reset : std_logic;
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------------------------------------------------------------------------
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------------------------------------------------------------------------
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------ GPIB interface --------------------------------------------------
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------ GPIB interface --------------------------------------------------
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------------------------------------------------------------------------
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------------------------------------------------------------------------
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-- input data
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-- input data
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data_in : in std_logic_vector (7 downto 0);
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data_in : in std_logic_vector (7 downto 0);
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-- data valid
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-- data valid
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dvd : in std_logic;
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dvd : in std_logic;
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-- listener active
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-- listener active
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lac : in std_logic;
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lac : in std_logic;
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-- last byte
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-- last byte
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lsb : in std_logic;
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lsb : in std_logic;
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-- ready to next byte
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-- ready to next byte
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rdy : out std_logic;
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rdy : out std_logic;
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------------------------------------------------------------------------
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------------------------------------------------------------------------
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------ external interface ----------------------------------------------
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------ external interface ----------------------------------------------
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------------------------------------------------------------------------
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------------------------------------------------------------------------
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-- is LE function active
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-- is LE function active
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isLE : in std_logic;
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isLE : in std_logic;
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-- current secondary address
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-- current secondary address
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secAddr : in std_logic_vector (4 downto 0);
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secAddr : in std_logic_vector (4 downto 0);
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-- secondary address of data
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-- secondary address of data
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dataSecAddr : out std_logic_vector (4 downto 0);
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dataSecAddr : out std_logic_vector (4 downto 0);
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-- buffer ready interrupt
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-- buffer ready interrupt
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buf_interrupt : out std_logic;
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buf_interrupt : out std_logic;
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-- indicates end of stream
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-- indicates end of stream
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end_of_stream : out std_logic;
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end_of_stream : out std_logic;
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-- resets reader
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-- resets reader
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reset_reader : in std_logic;
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reset_reader : in std_logic;
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------------------ fifo --------------------------------------
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------------------ fifo --------------------------------------
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-- indicates fifo full
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-- indicates fifo full
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fifo_full : in std_logic;
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fifo_full : in std_logic;
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-- indicates fifo ready to write
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-- indicates fifo ready to write
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fifo_ready_to_write : in std_logic;
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fifo_ready_to_write : in std_logic;
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-- indicates at least one byte in fifo
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-- indicates at least one byte in fifo
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at_least_one_byte_in_fifo : in std_logic;
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at_least_one_byte_in_fifo : in std_logic;
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-- output data
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-- output data
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data_out : out std_logic_vector (7 downto 0);
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data_out : out std_logic_vector (7 downto 0);
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-- fifo strobe
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-- fifo strobe
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fifo_strobe : out std_logic
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fifo_strobe : out std_logic
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);
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);
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end gpibReader;
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end gpibReader;
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architecture arch of gpibReader is
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architecture arch of gpibReader is
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-- reader states
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-- reader states
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type READER_STATE is (
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type READER_STATE is (
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ST_IDLE,
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ST_IDLE,
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ST_WAIT_DVD_1,
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ST_WAIT_DVD_1,
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ST_WAIT_DVD_0
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ST_WAIT_DVD_0
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);
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);
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signal current_state : READER_STATE;
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signal current_state : READER_STATE;
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signal buf_ready_to_write : boolean;
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signal buf_ready_to_write : boolean;
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begin
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begin
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buf_interrupt <= not to_stdl(buf_ready_to_write);
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buf_interrupt <= not to_stdl(buf_ready_to_write);
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process (clk, reset, reset_reader) begin
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process (clk, reset, reset_reader) begin
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if reset = '1' then
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if reset = '1' then
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current_state <= ST_IDLE;
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current_state <= ST_IDLE;
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rdy <= '1';
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rdy <= '1';
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buf_ready_to_write <= TRUE;
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buf_ready_to_write <= TRUE;
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end_of_stream <= '0';
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end_of_stream <= '0';
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fifo_strobe <= '0';
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fifo_strobe <= '0';
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dataSecAddr <= "00000";
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dataSecAddr <= "00000";
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elsif reset_reader='1' then
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elsif reset_reader='1' then
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buf_ready_to_write <= TRUE;
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buf_ready_to_write <= TRUE;
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end_of_stream <= '0';
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end_of_stream <= '0';
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fifo_strobe <= '0';
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fifo_strobe <= '0';
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dataSecAddr <= "00000";
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dataSecAddr <= "00000";
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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case current_state is
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case current_state is
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when ST_IDLE =>
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when ST_IDLE =>
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if lac='1' and buf_ready_to_write then
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if lac='1' and buf_ready_to_write then
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if isLE = '1' then
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if isLE = '1' then
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dataSecAddr <= secAddr;
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dataSecAddr <= secAddr;
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end if;
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end if;
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rdy <= '1';
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rdy <= '1';
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current_state <= ST_WAIT_DVD_1;
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current_state <= ST_WAIT_DVD_1;
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elsif lac='0' and at_least_one_byte_in_fifo='1' then
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elsif lac='0' and at_least_one_byte_in_fifo='1' then
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buf_ready_to_write <= FALSE;
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buf_ready_to_write <= FALSE;
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end if;
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end if;
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when ST_WAIT_DVD_1 =>
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when ST_WAIT_DVD_1 =>
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if dvd='1' and fifo_ready_to_write='1' then
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if dvd='1' and fifo_ready_to_write='1' then
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fifo_strobe <= '1';
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fifo_strobe <= '1';
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data_out <= data_in;
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data_out <= data_in;
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if lsb='1'or fifo_full='1' then
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if lsb='1'or fifo_full='1' then
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buf_ready_to_write <= FALSE;
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buf_ready_to_write <= FALSE;
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end_of_stream <= lsb;
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end_of_stream <= lsb;
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end if;
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end if;
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rdy <= '0';
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rdy <= '0';
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current_state <= ST_WAIT_DVD_0;
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current_state <= ST_WAIT_DVD_0;
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elsif lac='0' then
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elsif lac='0' then
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current_state <= ST_IDLE;
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current_state <= ST_IDLE;
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end if;
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end if;
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when ST_WAIT_DVD_0 =>
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when ST_WAIT_DVD_0 =>
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if dvd='0' then
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if dvd='0' then
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fifo_strobe <= '0';
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fifo_strobe <= '0';
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current_state <= ST_IDLE;
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current_state <= ST_IDLE;
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end if;
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end if;
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when others =>
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when others =>
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current_state <= ST_IDLE;
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current_state <= ST_IDLE;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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end arch;
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end arch;
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