--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Company:
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--This file is part of fpga_gpib_controller.
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-- Engineer:
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--
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-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- Fpga_gpib_controller is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
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--------------------------------------------------------------------------------
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-- Author: Andrzej Paluch
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--
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--
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-- Create Date: 16:22:23 02/04/2012
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-- Create Date: 16:22:23 02/04/2012
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-- Design Name:
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-- Design Name:
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-- Module Name: /home/andrzej/apaluch/projects/elektronika/GPIB/vhdl/test/RegsGpibFasade_test.vhd
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-- Module Name: RegsGpibFasade_test.vhd
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-- Project Name: proto1
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-- Project Name: proto1
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-- Target Device:
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-- Target Device:
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-- Tool versions:
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-- Tool versions:
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-- Description:
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-- Description:
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--
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--
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-- VHDL Test Bench Created by ISE for module: RegsGpibFasade
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-- VHDL Test Bench Created by ISE for module: RegsGpibFasade
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--
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--
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-- Dependencies:
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-- Dependencies:
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--
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--
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-- Revision:
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-- Revision:
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-- Revision 0.01 - File Created
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-- Revision 0.01 - File Created
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-- Additional Comments:
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-- Additional Comments:
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--
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--
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-- Notes:
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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-- simulation model.
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_1164.ALL;
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-- Uncomment the following library declaration if using
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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-- arithmetic functions with Signed or Unsigned values
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--USE ieee.numeric_std.ALL;
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--USE ieee.numeric_std.ALL;
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use work.wrapperComponents.ALL;
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use work.wrapperComponents.ALL;
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ENTITY RegsGpibFasade_test IS
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ENTITY RegsGpibFasade_test IS
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END RegsGpibFasade_test;
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END RegsGpibFasade_test;
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ARCHITECTURE behavior OF RegsGpibFasade_test IS
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ARCHITECTURE behavior OF RegsGpibFasade_test IS
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component gpibCableEmulator is port (
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component gpibCableEmulator is port (
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-- interface signals
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-- interface signals
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DIO_1 : in std_logic_vector (7 downto 0);
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DIO_1 : in std_logic_vector (7 downto 0);
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output_valid_1 : in std_logic;
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output_valid_1 : in std_logic;
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DIO_2 : in std_logic_vector (7 downto 0);
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DIO_2 : in std_logic_vector (7 downto 0);
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output_valid_2 : in std_logic;
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output_valid_2 : in std_logic;
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DIO : out std_logic_vector (7 downto 0);
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DIO : out std_logic_vector (7 downto 0);
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-- attention
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-- attention
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ATN_1 : in std_logic;
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ATN_1 : in std_logic;
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ATN_2 : in std_logic;
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ATN_2 : in std_logic;
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ATN : out std_logic;
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ATN : out std_logic;
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-- data valid
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-- data valid
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DAV_1 : in std_logic;
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DAV_1 : in std_logic;
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DAV_2 : in std_logic;
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DAV_2 : in std_logic;
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DAV : out std_logic;
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DAV : out std_logic;
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-- not ready for data
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-- not ready for data
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NRFD_1 : in std_logic;
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NRFD_1 : in std_logic;
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NRFD_2 : in std_logic;
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NRFD_2 : in std_logic;
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NRFD : out std_logic;
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NRFD : out std_logic;
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-- no data accepted
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-- no data accepted
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NDAC_1 : in std_logic;
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NDAC_1 : in std_logic;
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NDAC_2 : in std_logic;
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NDAC_2 : in std_logic;
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NDAC : out std_logic;
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NDAC : out std_logic;
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-- end or identify
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-- end or identify
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EOI_1 : in std_logic;
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EOI_1 : in std_logic;
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EOI_2 : in std_logic;
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EOI_2 : in std_logic;
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EOI : out std_logic;
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EOI : out std_logic;
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-- service request
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-- service request
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SRQ_1 : in std_logic;
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SRQ_1 : in std_logic;
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SRQ_2 : in std_logic;
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SRQ_2 : in std_logic;
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SRQ : out std_logic;
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SRQ : out std_logic;
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-- interface clear
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-- interface clear
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IFC_1 : in std_logic;
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IFC_1 : in std_logic;
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IFC_2 : in std_logic;
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IFC_2 : in std_logic;
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IFC : out std_logic;
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IFC : out std_logic;
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-- remote enable
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-- remote enable
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REN_1 : in std_logic;
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REN_1 : in std_logic;
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REN_2 : in std_logic;
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REN_2 : in std_logic;
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REN : out std_logic
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REN : out std_logic
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);
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);
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end component;
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end component;
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--Inputs
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--Inputs
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signal reset : std_logic := '0';
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signal reset : std_logic := '0';
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signal clk : std_logic := '0';
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signal clk : std_logic := '0';
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signal DI : std_logic_vector(7 downto 0) := (others => '0');
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signal DI : std_logic_vector(7 downto 0) := (others => '0');
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signal ATN_in : std_logic := '0';
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signal ATN_in : std_logic := '0';
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signal DAV_in : std_logic := '0';
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signal DAV_in : std_logic := '0';
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signal NRFD_in : std_logic := '0';
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signal NRFD_in : std_logic := '0';
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signal NDAC_in : std_logic := '0';
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signal NDAC_in : std_logic := '0';
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signal EOI_in : std_logic := '0';
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signal EOI_in : std_logic := '0';
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signal SRQ_in : std_logic := '0';
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signal SRQ_in : std_logic := '0';
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signal IFC_in : std_logic := '0';
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signal IFC_in : std_logic := '0';
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signal REN_in : std_logic := '0';
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signal REN_in : std_logic := '0';
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signal data_in : std_logic_vector(15 downto 0) := (others => '0');
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signal data_in : std_logic_vector(15 downto 0) := (others => '0');
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signal reg_addr : std_logic_vector(14 downto 0) := (others => '0');
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signal reg_addr : std_logic_vector(14 downto 0) := (others => '0');
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signal strobe_read : std_logic := '0';
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signal strobe_read : std_logic := '0';
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signal strobe_write : std_logic := '0';
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signal strobe_write : std_logic := '0';
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--Outputs
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--Outputs
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signal DO : std_logic_vector(7 downto 0);
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signal DO : std_logic_vector(7 downto 0);
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signal output_valid : std_logic;
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signal output_valid : std_logic;
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signal ATN_out : std_logic;
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signal ATN_out : std_logic;
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signal DAV_out : std_logic;
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signal DAV_out : std_logic;
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signal NRFD_out : std_logic;
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signal NRFD_out : std_logic;
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signal NDAC_out : std_logic;
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signal NDAC_out : std_logic;
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signal EOI_out : std_logic;
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signal EOI_out : std_logic;
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signal SRQ_out : std_logic;
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signal SRQ_out : std_logic;
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signal IFC_out : std_logic;
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signal IFC_out : std_logic;
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signal REN_out : std_logic;
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signal REN_out : std_logic;
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signal data_out : std_logic_vector(15 downto 0);
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signal data_out : std_logic_vector(15 downto 0);
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signal interrupt_line : std_logic;
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signal interrupt_line : std_logic;
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signal debug1 : std_logic;
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signal debug1 : std_logic;
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-- Clock period definitions
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-- Clock period definitions
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constant clk_period : time := 10 ns;
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constant clk_period : time := 10 ns;
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BEGIN
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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-- Instantiate the Unit Under Test (UUT)
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uut: RegsGpibFasade PORT MAP (
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uut: RegsGpibFasade PORT MAP (
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reset => reset,
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reset => reset,
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clk => clk,
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clk => clk,
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DI => DI,
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DI => DI,
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DO => DO,
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DO => DO,
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output_valid => output_valid,
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output_valid => output_valid,
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ATN_in => ATN_in,
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ATN_in => ATN_in,
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ATN_out => ATN_out,
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ATN_out => ATN_out,
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DAV_in => DAV_in,
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DAV_in => DAV_in,
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DAV_out => DAV_out,
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DAV_out => DAV_out,
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NRFD_in => NRFD_in,
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NRFD_in => NRFD_in,
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NRFD_out => NRFD_out,
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NRFD_out => NRFD_out,
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NDAC_in => NDAC_in,
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NDAC_in => NDAC_in,
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NDAC_out => NDAC_out,
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NDAC_out => NDAC_out,
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EOI_in => EOI_in,
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EOI_in => EOI_in,
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EOI_out => EOI_out,
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EOI_out => EOI_out,
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SRQ_in => SRQ_in,
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SRQ_in => SRQ_in,
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SRQ_out => SRQ_out,
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SRQ_out => SRQ_out,
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IFC_in => IFC_in,
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IFC_in => IFC_in,
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IFC_out => IFC_out,
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IFC_out => IFC_out,
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REN_in => REN_in,
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REN_in => REN_in,
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REN_out => REN_out,
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REN_out => REN_out,
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data_in => data_in,
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data_in => data_in,
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data_out => data_out,
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data_out => data_out,
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reg_addr => reg_addr,
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reg_addr => reg_addr,
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strobe_read => strobe_read,
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strobe_read => strobe_read,
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strobe_write => strobe_write,
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strobe_write => strobe_write,
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interrupt_line => interrupt_line,
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interrupt_line => interrupt_line,
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debug1 => debug1
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debug1 => debug1
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);
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);
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gce: gpibCableEmulator port map (
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gce: gpibCableEmulator port map (
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-- interface signals
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-- interface signals
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DIO_1 => DO,
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DIO_1 => DO,
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output_valid_1 => output_valid,
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output_valid_1 => output_valid,
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DIO_2 => "00000000",
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DIO_2 => "00000000",
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output_valid_2 => '0',
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output_valid_2 => '0',
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DIO => DI,
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DIO => DI,
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-- attention
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-- attention
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ATN_1 => ATN_out,
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ATN_1 => ATN_out,
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ATN_2 => '0',
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ATN_2 => '0',
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ATN => ATN_in,
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ATN => ATN_in,
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-- data valid
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-- data valid
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DAV_1 => DAV_out,
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DAV_1 => DAV_out,
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DAV_2 => '0',
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DAV_2 => '0',
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DAV => DAV_in,
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DAV => DAV_in,
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-- not ready for data
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-- not ready for data
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NRFD_1 => NRFD_out,
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NRFD_1 => NRFD_out,
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NRFD_2 => '0',
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NRFD_2 => '0',
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NRFD => NRFD_in,
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NRFD => NRFD_in,
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-- no data accepted
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-- no data accepted
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NDAC_1 => NDAC_out,
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NDAC_1 => NDAC_out,
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NDAC_2 => '0',
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NDAC_2 => '0',
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NDAC => NDAC_in,
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NDAC => NDAC_in,
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-- end or identify
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-- end or identify
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EOI_1 => EOI_out,
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EOI_1 => EOI_out,
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EOI_2 => '0',
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EOI_2 => '0',
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EOI => EOI_in,
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EOI => EOI_in,
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-- service request
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-- service request
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SRQ_1 => SRQ_out,
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SRQ_1 => SRQ_out,
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SRQ_2 => '0',
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SRQ_2 => '0',
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SRQ => SRQ_in,
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SRQ => SRQ_in,
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-- interface clear
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-- interface clear
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IFC_1 => IFC_out,
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IFC_1 => IFC_out,
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IFC_2 => '0',
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IFC_2 => '0',
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IFC => IFC_in,
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IFC => IFC_in,
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-- remote enable
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-- remote enable
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REN_1 => REN_out,
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REN_1 => REN_out,
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REN_2 => '0',
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REN_2 => '0',
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REN => REN_in
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REN => REN_in
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);
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);
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-- Clock process definitions
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-- Clock process definitions
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clk_process :process
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clk_process :process
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begin
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begin
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clk <= '0';
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clk <= '0';
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wait for clk_period/2;
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wait for clk_period/2;
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clk <= '1';
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clk <= '1';
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wait for clk_period/2;
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wait for clk_period/2;
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end process;
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end process;
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-- Stimulus process
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-- Stimulus process
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stim_proc: process begin
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stim_proc: process begin
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-- hold reset state for 10 clock cycles
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-- hold reset state for 10 clock cycles
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reset <= '1';
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reset <= '1';
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wait for clk_period*10;
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wait for clk_period*10;
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reset <= '0';
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reset <= '0';
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wait for clk_period*10;
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wait for clk_period*10;
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-- set rsc
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-- set rsc
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reg_addr <= "000000000000111";
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reg_addr <= "000000000000111";
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data_in <= "0000000001000000";
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data_in <= "0000000001000000";
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wait for clk_period*2;
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wait for clk_period*2;
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strobe_write <= '1';
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strobe_write <= '1';
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wait for clk_period*2;
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wait for clk_period*2;
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strobe_write <= '0';
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strobe_write <= '0';
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wait for clk_period*20;
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wait for clk_period*20;
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-- set sic
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-- set sic
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data_in <= "0000000011000000";
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data_in <= "0000000011000000";
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wait for clk_period*2;
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wait for clk_period*2;
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strobe_write <= '1';
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strobe_write <= '1';
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wait for clk_period*2;
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wait for clk_period*2;
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strobe_write <= '0';
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strobe_write <= '0';
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wait for clk_period*20;
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wait for clk_period*20;
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-- reset sic
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-- reset sic
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data_in <= "0000000001000000";
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data_in <= "0000000001000000";
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wait for clk_period*2;
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wait for clk_period*2;
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strobe_write <= '1';
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strobe_write <= '1';
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wait for clk_period*2;
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wait for clk_period*2;
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strobe_write <= '0';
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strobe_write <= '0';
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wait for clk_period*20;
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wait for clk_period*20;
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-- enable writer
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-- enable writer
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reg_addr <= "000000000001010";
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reg_addr <= "000000000001010";
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data_in <= "0000000000000010";
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data_in <= "0000000000000010";
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wait for clk_period*2;
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wait for clk_period*2;
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strobe_write <= '1';
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strobe_write <= '1';
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wait for clk_period*2;
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wait for clk_period*2;
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strobe_write <= '0';
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strobe_write <= '0';
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-- self address to listen
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-- self address to listen
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reg_addr <= "000000000001101";
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reg_addr <= "000000000001101";
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data_in <= "0000000000100001";
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data_in <= "0000000000100001";
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wait for clk_period*2;
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wait for clk_period*2;
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strobe_write <= '1';
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strobe_write <= '1';
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wait for clk_period*2;
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wait for clk_period*2;
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strobe_write <= '0';
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strobe_write <= '0';
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-- self address to listen again
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-- self address to listen again
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reg_addr <= "000000000001101";
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reg_addr <= "000000000001101";
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data_in <= "0000000000100011";
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data_in <= "0000000000100011";
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wait for clk_period*2;
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wait for clk_period*2;
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strobe_write <= '1';
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strobe_write <= '1';
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wait for clk_period*2;
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wait for clk_period*2;
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strobe_write <= '0';
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strobe_write <= '0';
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wait for clk_period*10;
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wait for clk_period*10;
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wait;
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wait;
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end process;
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end process;
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END;
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END;
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