-- Filename: example_driver.vhd
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-- Filename: example_driver.vhd
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-- Filetype: VHDL Source Code
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-- Filetype: VHDL Source Code
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-- Date: 26 oct 2012
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-- Date: 26 oct 2012
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-- Update: -
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-- Update: -
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-- Description: VHDL Description of example driver
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-- Description: VHDL Description of example driver
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-- Author: J. op den Brouw
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-- Author: J. op den Brouw
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-- State: Demo
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-- State: Demo
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-- Error: -
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-- Error: -
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-- Version: 1.1alpha
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-- Version: 1.1alpha
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-- Copyright: (c)2012, De Haagse Hogeschool
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-- Copyright: (c)2012, De Haagse Hogeschool
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-- This VHDL code is a example description on how to use the
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-- This VHDL code is a example description on how to use the
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-- HD44780 LCD display driver module. It writes 4x16 characters
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-- HD44780 LCD display driver module. It writes 4x16 characters
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-- to the display, presuming that the display has four lines.
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-- to the display, presuming that the display has four lines.
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--
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--
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-- This code is tested on a Terasic DE0-board with an optional
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-- This code is tested on a Terasic DE0-board with an optional
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-- LCD display. See the weblinks
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-- LCD display. See the weblinks
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-- http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=56&No=364
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-- http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=56&No=364
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-- http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=78&No=396
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-- http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=78&No=396
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-- for more info. The display used has only two lines.
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-- for more info. The display used has only two lines.
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-- After a line has written completely, the cursor is moved to
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-- After a line has written completely, the cursor is moved to
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-- the beginning of the next line. After the last line is written,
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-- the beginning of the next line. After the last line is written,
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-- this code goes into hold mode.
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-- this code goes into hold mode.
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--
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--
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-- Libraries et al.
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-- Libraries et al.
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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-- The entity of a Terasic DE0-board.
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-- The entity of a Terasic DE0-board.
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entity example_driver is
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entity example_driver is
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port (CLOCK_50 : in std_logic;
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port (CLOCK_50 : in std_logic;
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BUTTON : in std_logic_vector(2 downto 0);
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BUTTON : in std_logic_vector(2 downto 0);
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SW : in std_logic_vector(9 downto 0);
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SW : in std_logic_vector(9 downto 0);
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LEDG : out std_logic_vector(9 downto 0);
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LEDG : out std_logic_vector(9 downto 0);
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HEX3_D : out std_logic_vector(6 downto 0);
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HEX3_D : out std_logic_vector(6 downto 0);
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HEX2_D : out std_logic_vector(6 downto 0);
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HEX2_D : out std_logic_vector(6 downto 0);
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HEX1_D : out std_logic_vector(6 downto 0);
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HEX1_D : out std_logic_vector(6 downto 0);
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HEX0_D : out std_logic_vector(6 downto 0);
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HEX0_D : out std_logic_vector(6 downto 0);
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HEX0_DP : out std_logic;
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HEX0_DP : out std_logic;
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HEX1_DP : out std_logic;
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HEX1_DP : out std_logic;
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HEX2_DP : out std_logic;
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HEX2_DP : out std_logic;
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HEX3_DP : out std_logic;
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HEX3_DP : out std_logic;
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-- LCD of the DE0 board
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-- LCD of the DE0 board
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LCD_EN : out std_logic;
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LCD_EN : out std_logic;
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LCD_RS : out std_logic;
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LCD_RS : out std_logic;
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LCD_RW : out std_logic;
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LCD_RW : out std_logic;
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LCD_DATA : inout std_logic_vector(7 downto 0);
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LCD_DATA : inout std_logic_vector(7 downto 0);
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LCD_BLON : out std_logic
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LCD_BLON : out std_logic
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);
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);
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end entity example_driver;
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end entity example_driver;
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-- The architecture!
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-- The architecture!
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architecture hardware of example_driver is
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architecture hardware of example_driver is
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-- Component declaration of the LCD module
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-- Component declaration of the LCD module
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component lcd_driver_hd44780_module is
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component lcd_driver_hd44780_module is
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generic (freq : integer := 50000000;
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generic (freq : integer := 50000000;
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areset_pol : std_logic := '1';
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areset_pol : std_logic := '1';
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time_init1 : time := 40 ms;
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time_init1 : time := 40 ms;
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time_init2 : time := 4100 us;
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time_init2 : time := 4100 us;
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time_init3 : time := 100 us;
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time_init3 : time := 100 us;
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time_tas : time := 60 ns;
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time_tas : time := 60 ns;
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time_cycle_e : time := 1000 ns;
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time_cycle_e : time := 1000 ns;
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time_pweh : time := 500 ns;
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time_pweh : time := 500 ns;
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time_no_bf : time := 2 ms;
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time_no_bf : time := 2 ms;
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cursor_on : boolean := false;
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cursor_on : boolean := false;
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blink_on : boolean := false;
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blink_on : boolean := false;
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use_bf : boolean := true
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use_bf : boolean := true
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);
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);
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port (clk : in std_logic;
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port (clk : in std_logic;
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areset : in std_logic;
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areset : in std_logic;
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-- User site
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-- User site
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init : in std_logic;
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init : in std_logic;
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data : in std_logic_vector(7 downto 0);
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data : in std_logic_vector(7 downto 0);
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wr : in std_logic;
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wr : in std_logic;
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cls : in std_logic;
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cls : in std_logic;
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home : in std_logic;
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home : in std_logic;
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goto10 : in std_logic;
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goto10 : in std_logic;
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goto20 : in std_logic;
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goto20 : in std_logic;
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goto30 : in std_logic;
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goto30 : in std_logic;
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busy : out std_logic;
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busy : out std_logic;
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-- LCD side
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-- LCD side
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LCD_E : out std_logic;
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LCD_E : out std_logic;
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LCD_RS : out std_logic;
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LCD_RS : out std_logic;
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LCD_RW : out std_logic;
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LCD_RW : out std_logic;
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LCD_DB : inout std_logic_vector(7 downto 0)
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LCD_DB : inout std_logic_vector(7 downto 0)
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);
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);
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end component lcd_driver_hd44780_module;
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end component lcd_driver_hd44780_module;
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-- The system's frequency
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-- The system's frequency
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constant sys_freq : integer := 50000000;
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constant sys_freq : integer := 50000000;
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signal areset : std_logic;
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signal areset : std_logic;
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signal clk : std_logic;
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signal clk : std_logic;
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signal init : std_logic;
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signal init : std_logic;
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signal data : std_logic_vector(7 downto 0);
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signal data : std_logic_vector(7 downto 0);
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signal wr : std_logic;
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signal wr : std_logic;
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signal cls : std_logic;
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signal cls : std_logic;
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signal home : std_logic;
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signal home : std_logic;
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signal goto10 : std_logic;
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signal goto10 : std_logic;
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signal goto20 : std_logic;
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signal goto20 : std_logic;
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signal goto30 : std_logic;
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signal goto30 : std_logic;
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signal busy : std_logic;
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signal busy : std_logic;
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type state_type is (reset, write_char, write_char_wait, update, update_linecount,
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type state_type is (reset, write_char, write_char_wait, update, update_linecount,
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update_linecount_wait, write_char_1, write_char_1_wait,
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update_linecount_wait, write_char_1, write_char_1_wait,
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write_char_2, write_char_2_wait, write_char_3, write_char_4, hold);
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write_char_2, write_char_2_wait, write_char_3, write_char_4, hold,
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hold2);
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signal state : state_type;
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signal state : state_type;
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-- A string of 16 characters
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-- A string of 16 characters
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subtype string16_type is string(1 to 16);
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subtype string16_type is string(1 to 16);
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-- An array of 4 strings of 16 characters.
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-- An array of 4 strings of 16 characters.
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type message4x16_type is array (1 to 4) of string16_type;
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type message4x16_type is array (1 to 4) of string16_type;
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-- The four-line message
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-- The four-line message
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constant message : message4x16_type :=
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constant message : message4x16_type :=
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( 1 => "1Elektrotechniek",
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( 1 => "1Elektrotechniek",
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2 => "2 LCD HD44780 ",
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2 => "2 LCD HD44780 ",
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3 => "3Driver in VHDL!",
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3 => "3Driver in VHDL!",
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4 => "4J. op den Brouw");
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4 => "4J. op den Brouw");
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-- Counts the characters on a line.
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-- Counts the characters on a line.
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signal character_counter : integer range 1 to 16;
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signal character_counter : integer range 1 to 16;
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-- Counts the lines.
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-- Counts the lines.
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signal line_counter : integer range 1 to 4;
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signal line_counter : integer range 1 to 4;
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begin
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begin
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-- Push buttons are active low.
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-- Push buttons are active low.
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areset <= not BUTTON(0);
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areset <= not BUTTON(0);
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-- The clock
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-- The clock
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clk <= CLOCK_50;
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clk <= CLOCK_50;
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-- Use LCD module.
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-- Use LCD module.
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lcdm : lcd_driver_hd44780_module
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lcdm : lcd_driver_hd44780_module
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generic map (freq => sys_freq, areset_pol => '1', time_cycle_e => 2000 ns, time_pweh => 500 ns,
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generic map (freq => sys_freq, areset_pol => '1', time_cycle_e => 2000 ns, time_pweh => 500 ns,
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cursor_on => false, blink_on => false, use_bf => false)
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cursor_on => false, blink_on => false, use_bf => false)
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port map (clk => clk, areset => areset, init => init, data => data, wr => wr, cls => cls,
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port map (clk => clk, areset => areset, init => init, data => data, wr => wr, cls => cls,
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home => home, goto10 => goto10, goto20 => goto20, goto30 => goto30, busy => busy,
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home => home, goto10 => goto10, goto20 => goto20, goto30 => goto30, busy => busy,
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LCD_E => LCD_EN, LCD_RS => LCD_RS, LCD_RW => LCD_RW, LCD_DB => LCD_DATA);
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LCD_E => LCD_EN, LCD_RS => LCD_RS, LCD_RW => LCD_RW, LCD_DB => LCD_DATA);
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-- The client side
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-- The client side
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drive: process (clk, areset) is
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drive: process (clk, areset) is
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variable aline : string16_type;
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variable aline : string16_type;
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begin
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begin
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if areset = '1' then
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if areset = '1' then
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wr <= '0';
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wr <= '0';
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init <= '0';
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init <= '0';
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cls <= '0';
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cls <= '0';
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home <= '0';
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home <= '0';
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goto10 <= '0';
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goto10 <= '0';
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goto20 <= '0';
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goto20 <= '0';
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goto30 <= '0';
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goto30 <= '0';
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LEDG(0) <= '0';
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LEDG(0) <= '0';
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data <= "00000000";
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data <= "00000000";
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character_counter <= 1;
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character_counter <= 1;
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state <= reset;
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state <= reset;
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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wr <= '0';
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wr <= '0';
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init <= '0';
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init <= '0';
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cls <= '0';
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cls <= '0';
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home <= '0';
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home <= '0';
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goto10 <= '0';
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goto10 <= '0';
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goto20 <= '0';
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goto20 <= '0';
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goto30 <= '0';
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goto30 <= '0';
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LEDG(0) <= '0';
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LEDG(0) <= '0';
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data <= "00000000";
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data <= "00000000";
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case state is
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case state is
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when reset =>
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when reset =>
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-- Wait for the LCD module ready
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-- Wait for the LCD module ready
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if busy = '0' then
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if busy = '0' then
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state <= write_char;
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state <= write_char;
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end if;
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end if;
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-- Setup message counter, start at 1.
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-- Setup message counter, start at 1.
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character_counter <= 1;
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character_counter <= 1;
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line_counter <= 1;
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line_counter <= 1;
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when write_char =>
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when write_char =>
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LEDG(0) <= '1';
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LEDG(0) <= '1';
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-- Set up WRITE!
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-- Set up WRITE!
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-- Use the data from the string
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-- Use the data from the string
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aline := message(line_counter);
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aline := message(line_counter);
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data <= std_logic_vector( to_unsigned( character'pos(aline(character_counter)),8));
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data <= std_logic_vector( to_unsigned( character'pos(aline(character_counter)),8));
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wr <= '1';
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wr <= '1';
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state <= write_char_wait;
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state <= write_char_wait;
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when write_char_wait =>
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when write_char_wait =>
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-- This state is needed so that the LCD driver
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-- This state is needed so that the LCD driver
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-- can process the write command. Note that data
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-- can process the write command. Note that data
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-- and wr are registered outputs and get their
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-- and wr are registered outputs and get their
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-- respective values while in *this* state. If you don't
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-- respective values while in *this* state. If you don't
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-- want this behaviour, please make your outputs
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-- want this behaviour, please make your outputs
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-- non-registered.
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-- non-registered.
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state <= update;
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state <= update;
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when update =>
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when update =>
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LEDG(0) <= '1';
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LEDG(0) <= '1';
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-- Wait for the write complete
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-- Wait for the write complete
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if busy = '0' then
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if busy = '0' then
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-- If end of string, goto hold mode...
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-- If end of string, goto hold mode...
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if line_counter = 4 and character_counter = 16 then
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if line_counter = 4 and character_counter = 16 then
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state <= hold;
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state <= hold;
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-- If end of line...
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-- If end of line...
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elsif character_counter = 16 then
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elsif character_counter = 16 then
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case line_counter is
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case line_counter is
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when 1 => goto10 <= '1';
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when 1 => goto10 <= '1';
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when 2 => goto20 <= '1';
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when 2 => goto20 <= '1';
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when 3 => goto30 <= '1';
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when 3 => goto30 <= '1';
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-- Never reached, but nice anyway...
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-- Never reached, but nice anyway...
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when 4 => home <= '1';
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when 4 => home <= '1';
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when others => null;
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when others => null;
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end case;
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end case;
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-- Set new values of the counters
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-- Set new values of the counters
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line_counter <= line_counter+1;
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line_counter <= line_counter+1;
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character_counter <= 1;
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character_counter <= 1;
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-- Goto the update state
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-- Goto the update state
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state <= update_linecount;
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state <= update_linecount;
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else
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else
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-- Not the end of a lines, update the character counter.
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-- Not the end of a lines, update the character counter.
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character_counter <= character_counter+1;
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character_counter <= character_counter+1;
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state <= write_char;
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state <= write_char;
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end if;
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end if;
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end if;
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end if;
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when update_linecount =>
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when update_linecount =>
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-- This state is needed so that the LCD driver
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-- This state is needed so that the LCD driver
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-- can process the gotoXX command. Note that the gotoXX
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-- can process the gotoXX command. Note that the gotoXX
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-- signals are registered outputs and get their
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-- signals are registered outputs and get their
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-- respective values while in *this* state. If you don't
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-- respective values while in *this* state. If you don't
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-- want this behaviour, please make your outputs
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-- want this behaviour, please make your outputs
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-- non-registered.
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-- non-registered.
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state <= update_linecount_wait;
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state <= update_linecount_wait;
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when update_linecount_wait =>
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when update_linecount_wait =>
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-- Wait for the LCD module ready
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-- Wait for the LCD module ready
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if busy = '0' then
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if busy = '0' then
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state <= write_char;
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state <= write_char;
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end if;
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end if;
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-- The "hohouwer"
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-- The "hohouwer"
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when hold =>
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when hold =>
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state <= hold;
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--state <= hold;
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state <= hold2;
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home <= '1';
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when hold2 =>
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state <= reset;
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when others =>
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when others =>
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null;
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null;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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-- The unused outputs...
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-- The unused outputs...
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HEX3_D <= (others => '1');
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HEX3_D <= (others => '1');
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HEX2_D <= (others => '1');
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HEX2_D <= (others => '1');
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HEX1_D <= (others => '1');
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HEX1_D <= (others => '1');
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HEX0_D <= (others => '1');
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HEX0_D <= (others => '1');
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HEX3_DP <= '1';
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HEX3_DP <= '1';
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HEX2_DP <= '1';
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HEX2_DP <= '1';
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HEX1_DP <= '1';
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HEX1_DP <= '1';
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HEX0_DP <= '1';
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HEX0_DP <= '1';
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LEDG(9 downto 1) <= (others => '0');
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LEDG(9 downto 1) <= (others => '0');
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-- Sadly, the LCD doesn't have a backlight...
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-- Sadly, the LCD doesn't have a backlight...
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LCD_BLON <= '0';
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LCD_BLON <= '0';
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